PWM_CLKPSC (CLKPSC)

PWM_CMPDAT0 (CMPDAT0)

PWM_CNT0 (CNT0)

PERIOD1

CMPDAT1

CNT1

PWM_CLKDIV (CLKDIV)

PWM_INTEN (INTEN)

PWM_INTSTS (INTSTS)

PWM_CAPCTL01 (CAPCTL01)

PWM_RCAPDAT0 (RCAPDAT0)

PWM_FCAPDAT0 (FCAPDAT0)

RCAPDAT1

FCAPDAT1

PWM_CAPINEN (CAPINEN)

PWM_POEN (POEN)

PWM_CTL (CTL)

PWM_PERIOD0 (PERIOD0)

CLKPSC01 : Clock Pre-scaler Clock input is divided by (CLKPSC01 + 1). If CLKPSC01 aaa 0, then the pre-scaler output clock will be stopped. This implies PWM counter 0 and 1 will also be stopped.
bits : 0 - 7 (8 bit)
access : read-write

DTCNT01 : Dead Zone Interval Register For Pair Of PWM0 And PWM1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write

CMP : PWM Comparator Register CMP determines the PWM duty cycle. PWM frequency aaa PWM01_CLK/(prescale+1)*(clock divider)/(PERIOD+1) Duty Cycle aaa (CMP+1)/(PERIOD+1). CMP > aaa PERIOD: PWM output is always high. CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit. CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit (Unit aaa one PWM clock cycle) Note: Any write to CMP will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CNT : PWM Data Register Reports the current value of the 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CLKDIV0 : Timer 0 Clock Source Selection (Table is as CLKDIV1)
bits : 0 - 2 (3 bit)
access : read-write

CLKDIV1 : Timer 1 Clock Source Selection Value : Input clock divided by 0 : 2 1 : 4 2 : 8 3 : 16 4 : 1
bits : 4 - 6 (3 bit)
access : read-write

PIEN0 : PWM Timer 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN1 : PWM Timer 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF0 : PWM Timer 0 Interrupt Flag Flag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

PIF1 : PWM Timer 1 Interrupt Flag Flag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

CAPINV0 : Channel 0 Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN0 : Channel 0 Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN0 : Channel 0 Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN0 : Capture Channel 0 transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt is enabled (CRLIEN0 aaa 1), a rising transition at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt is enabled (CFLIEN0 aaa 1). This flag is cleared by software writing a '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

CRLIF0 : PWM_RCAPDAT0 Latched Indicator Bit When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLIF0 : PWM_FCAPDAT0 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 7 - 7 (1 bit)
access : read-write

CAPINV1 : Channel 1 Inverter ON/OFF
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN1 : Channel 1 Rising Latch Interrupt Enable When enabled, capture block generates an interrupt on rising edge of input.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN1 : Channel 1 Falling Latch Interrupt Enable When enabled, capture block generates an interrupt on falling edge of input.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN1 : Capture Channel 1 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt is enabled (CRLIEN1 aaa 1), a rising transition at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt is enabled (CFLIEN1 aaa 1). This flag is cleared by software writing a '1' to it.
bits : 20 - 20 (1 bit)
access : read-write

CRLIF1 : PWM_RCAPDAT1 Latched Indicator Bit When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLIF1 : PWM_FCAPDAT1 Latched Indicator Bit When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 23 - 23 (1 bit)
access : read-write

RCAPDAT : Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

FCAPDAT : Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

CAPINEN : Capture Input Enable Register 0 : OFF (PA[13:12] pin input disconnected from Capture block) 1 : ON (PA[13:12] pin, if in PWM alternative function, will be configured as an input and fed to capture function) CAPINEN[1:0] Bit 10 Bit x1 : Capture channel 0 is from PA [12] Bit 1x : Capture channel 1 is from PA [13]
bits : 0 - 1 (2 bit)
access : read-write

POEN0 : PWM0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN1 : PWM1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP Table 57)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : PWM-Timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : PWM-Timer 0 Output Inverter ON/OFF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : PWM-Timer 0 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEN01 : Dead-Zone 0 Generator Enable/Disable Note: When Dead-Zone Generator is enabled, the pair of PWM0 and PWM1 become a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM-Timer 1 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV1 : PWM-Timer 1 Output Inverter ON/OFF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE1 : PWM-Timer 1 Auto-reload/One-Shot Mode Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOD : PWM Counter/Timer Reload Value PERIOD determines the PWM period. PWM frequency aaa PWM01_CLK/(prescale+1)*(clock divider)/(PERIOD+1) Duty ratio aaa (CMP+1)/(PERIOD+1). CMP > aaa PERIOD: PWM output is always high. CMP < PERIOD: PWM low width aaa (PERIOD-CMP) unit PWM high width aaa (CMP+1) unit. CMP aaa 0: PWM low width aaa (PERIOD) unit PWM high width aaa 1 unit (Unit aaa one PWM clock cycle) Note: Any write to PERIOD will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write