Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GOBUSY : Go and Busy Status
NOTE: All registers should be set before writing 1 to this BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit starts the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished
End of enumeration elements list.
RXNET : Receive At Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data input signal is latched at the rising edge of SCLK
#1 : 1
The received data input signal is latched at the falling edge of SCLK
End of enumeration elements list.
TXNEG : Transmit At Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output signal is changed at the rising edge of SCLK
#1 : 1
The transmitted data output signal is changed at the falling edge of SCLK
End of enumeration elements list.
DWIDTH : Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
DWIDTH aaa 0x01 --- 1 bit
DWIDTH aaa 0x02 --- 2 bits
----
DWIDTH aaa 0x1f --- 31 bits
DWIDTH aaa 0x00 --- 32 bits
bits : 3 - 7 (5 bit)
access : read-write
TXNUM : Transmit/Receive Word Numbers
This field specifies how many transmit/receive word numbers should be executed in one transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive word will be executed in one transfer
#01 : 1
Two successive transmit/receive word will be executed in one transfer
#10 : 2
Reserved
#11 : 3
Reserved
End of enumeration elements list.
LSB : LSB First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first (which bit in SPI_TX0/1 and SPI_RX0/1 register that is depends on the DWIDTH field)
#1 : 1
The LSB is sent first on the line (bit 0 of SPI_TX0/1), and the first bit received from the line will be put in the LSB position in the Rx register (bit 0 of SPI_RX0/1)
End of enumeration elements list.
CLKPOL : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SCLK idle low
#1 : 1
SCLK idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Only)
These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL aaa 0. If CLKPOL aaa 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TXCNT aaa 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation:
(SUSPITV[3:0] + 2) * period of SCLK
bits : 12 - 15 (4 bit)
access : read-write
UNITIF : Interrupt Flag
NOTE: This bit is cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Indicates the transfer is not finished yet
#1 : 1
Indicates that the transfer is complete. Interrupt is generated to CPU if enabled
End of enumeration elements list.
UNITIEN : Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Interrupt
#1 : 1
Enable SPI Interrupt to CPU
End of enumeration elements list.
SLAVE : Master Slave Mode Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
BYTEITV : Insert Sleep Interval Between Bytes
This function is only valid for 32bit transfers (DWIDTH aaa 0). If set then a pause of (SUSPITV+2) SCLK cycles is inserted between each byte transmitted.
bits : 19 - 19 (1 bit)
access : read-write
REORDER : Byte Endian Reorder Function
This function changes the order of bytes sent/received to be least significant physical byte first.
bits : 20 - 20 (1 bit)
access : read-write
FIFOEN : FIFO Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No FIFO present on transmit and receive buffer
#1 : 1
Enable FIFO on transmit and receive buffer
End of enumeration elements list.
TWOBIT : Two Bits Transfer Mode
Note that when enabled in master mode, MOSI0 data comes from SPI_TX0 and MOSI1 data from SPI_TX1. Likewise SPI_RX0 receives bit stream from MISO0 and SPI_RX1 from MISO1. Note that when enabled, the setting of TXCNT must be programmed as 0x00
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable two-bit transfer mode
#1 : 1
Enable two-bit transfer mode
End of enumeration elements list.
VARCLKEN : Variable Clock Enable (Master Only)
Note that when enabled, the setting of DWIDTH must be programmed as 0x10 (16 bits mode)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The serial clock output frequency is fixed and determined only by the value of DIVIDER0
#1 : 1
SCLK output frequency is variable. The output frequency is determined by the value of SPI_VARCLK, DIVIDER0, and DIVIDER1
End of enumeration elements list.
RXEMPTY : Receive FIFO Empty Status
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive data FIFO is not empty
#1 : 1
The receive data FIFO is empty
End of enumeration elements list.
RXFULL : Receive FIFO Full Status
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive data FIFO is not full
#1 : 1
The receive data FIFO is full
End of enumeration elements list.
TXEMPTY : Transmit FIFO Empty Status
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit data FIFO is not empty
#1 : 1
The transmit data FIFO is empty
End of enumeration elements list.
TXFULL : Transmit FIFO Full Status
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit data FIFO is not full
#1 : 1
The transmit data FIFO is full
End of enumeration elements list.
PDMASSEN : Enable DMA Automatic SS function
When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.
bits : 28 - 28 (1 bit)
access : read-write
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CTL register. For example, if DWIDTH is set to 0x08 and TXCNT is set to 0x0, bit Rx0[7:0] holds the received data.
NOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the SPI_CTL register. For example, if DWIDTH is set to 0x08 and the TXCNT is set to 0x0, the bit TX0[7:0] will be transmitted in next transfer. If DWIDTH is set to 0x00 and TXCNT is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is TX0[31:0], TX1[31:0]).
bits : 0 - 31 (32 bit)
access : write-only
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Variable Clock Pattern Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern
The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER0. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER1. Refer to register DIVIDER0.
Refer to Variable Serial Clock Frequency paragraph for detailed description.
bits : 0 - 31 (32 bit)
access : read-write
SPI DMA Control Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPDMAEN : Transmit DMA Start
Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically.
If using DMA mode to transfer data, remember not to set BUSY bit of SPI_CTL register. The DMA controller inside SPI module will set it automatically whenever necessary.
bits : 0 - 0 (1 bit)
access : read-write
RXPDMAEN : Receive DMA Start
Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
bits : 1 - 1 (1 bit)
access : read-write
Clock Divider Register (Master Only)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER0 : Clock Divider Register (master only)
The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
Fsclk aaa Fpclk / ((DIVIDER0+1) * 2)
In slave mode, the period of SPI clock driven by a master shall satisfy
Fsclk < aaa (Fpclk / 5)
In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER1 : Clock Divider 2 Register (master only)
The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
Fsclk aaa Fpclk / ((DIVIDER1+1) * 2)
bits : 16 - 31 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Select Register (Master only)
If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state.
If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSACTPOL).
Note: SPISSx0 is always defined as device/slave select input signal in slave mode.
bits : 0 - 1 (2 bit)
access : read-write
SSACTPOL : Slave Select Active Level
It defines the active level of device/slave select signal (SPISSx0/1).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPISSx0/1 is active at low-level/falling-edge
#1 : 1
The slave select signal SPISSx0/1 is active at high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select (Master only)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals are asserted and de-asserted by setting and clearing related bits in SPI_SSCTL[1:0] register
#1 : 1
If this bit is set, SPISSx0/1 signals are generated automatically. It means that device/slave select signal, which is set in SPI_SSCTL[1:0] register is asserted by the SPI controller when transmit/receive is started by setting BUSY, and is de-asserted after each transmit/receive is finished
End of enumeration elements list.
LVTRGEN : Slave Select Level Trigger (Slave only)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger. This is the default value
#1 : 1
The slave select signal will be level-trigger. It depends on SSACTPOL to decide the signal is active low or active high
End of enumeration elements list.
LVTRGSTS : Level Trigger Flag
When the LVTRGEN bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not.
Note: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
One of the received number and the received bit length doesn't meet the requirement in one transfer
#1 : 1
The received number and received bits met the requirement which defines in TXCNT and DWIDTH among one transfer
End of enumeration elements list.
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