WDT_CTL (CTL)

RSTCNT : Clear Watchdog Timer Set this bit will clear the Watchdog timer. NOTE: This bit will auto clear after few clock cycle
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTEN : Watchdog Timer Reset Enable Setting this bit will enable the Watchdog timer reset function.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTF : Watchdog Timer Reset Flag When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit. NOTE: This bit is cleared by writing 1 to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IF : Watchdog Timer Interrupt Flag If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed. NOTE: This bit is cleared by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Watchdog Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTEN : Watchdog Timer Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTSEL : Watchdog Timer Interval Select These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by: Interrupt Timeout aaa 2^(2xWTIS+4) x WDT_CLK Reset Timeout aaa (2^(2xWTIS+4) +1024) x WDT_CLK Where WDT_CLK is the period of the Watchdog Timer clock source.
bits : 8 - 10 (3 bit)
access : read-write