\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
I2S Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SEN : Enable I2S Controller
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TXEN : Transmit Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable data transmit
#1 : 1
Enable data transmit
End of enumeration elements list.
RXEN : Receive Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable data receive
#1 : 1
Enable data receive
End of enumeration elements list.
MUTE : Transmit Mute Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit data is shifted from FIFO
#1 : 1
Transmit channel zero
End of enumeration elements list.
WDWIDTH : Word Width
This parameter sets the word width of audio data. See Figure 563 for details of how data is formatted in transmit and receive FIFO.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
data is 8 bit
#01 : 1
data is 16 bit
#10 : 2
data is 24 bit
#11 : 3
data is 32 bit
End of enumeration elements list.
MONO : Monaural data
This parameter sets whether mono or stereo data is processed. See Figure 563 for details of how data is formatted in transmit and receive FIFO.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data is stereo format
#1 : 1
Data is monaural format
End of enumeration elements list.
FORMAT : Data format
See Figure 561 and Figure 562 for timing differences.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2S data format
#1 : 1
MSB justified data format
End of enumeration elements list.
SLAVE : Slave Mode
I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from ISD91xx. In slave mode, I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
TXTH : Transmit FIFO Threshold Level
If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.
bits : 9 - 11 (3 bit)
access : read-write
RXTH : Receive FIFO Threshold Level
When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set.
bits : 12 - 14 (3 bit)
access : read-write
MCLKEN : Master Clock Enable
The ISD91xx can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the I2S_CLKDIV.MCLKDIV register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable master clock
#1 : 1
Enable master clock
End of enumeration elements list.
RZCEN : Right Channel Zero Cross Detect Enable
If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable right channel zero cross detect
#1 : 1
Enable right channel zero cross detect
End of enumeration elements list.
LZCEN : Left Channel Zero Cross Detect Enable
If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCIF flag in I2S_STATUS register will be set to 1.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable left channel zero cross detect
#1 : 1
Enable left channel zero cross detect
End of enumeration elements list.
TXCLR : Clear Transmit FIFO
Write 1 to clear transmitting FIFO, internal pointer is reset to FIFO start point, and TXTH returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed.
This bit is cleared by hardware automatically when clear operation complete.
bits : 18 - 18 (1 bit)
access : read-write
RXCLR : Clear Receive FIFO
Write 1 to clear receiving FIFO, internal pointer is reset to FIFO start point, and RXTH returns to zero and receive FIFO becomes empty.
This bit is cleared by hardware automatically when clear operation complete.
bits : 19 - 19 (1 bit)
access : read-write
TXPDMAEN : Enable Transmit DMA
When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TX DMA
#1 : 1
Enable TX DMA
End of enumeration elements list.
RXPDMAEN : Enable Receive DMA
When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RX DMA
#1 : 1
Enable RX DMA
End of enumeration elements list.
I2S Transmit FIFO Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Transmit FIFO Register (Write Only)
A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT.
bits : 0 - 31 (32 bit)
access : write-only
I2S Receive FIFO Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Receive FIFO Register (Read Only)
A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT.
bits : 0 - 31 (32 bit)
access : read-only
I2S Clock Divider Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCLKDIV : Master Clock Divider
ISD9160 can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLK clock input, otherwise MCLK frequency is given by:
F(MCLK) aaa F(I2S_CLK) / (2xMCLKDIV)
Or,
MCLKDIV aaa F(I2S_CLK) / (2 x F(MCLK))
If the desired MCLK frequency is 254Fs and Fs aaa 16kHz then MCLKDIV aaa 6
bits : 0 - 2 (3 bit)
access : read-write
BCLKDIV : Bit Clock Divider
If I2S operates in master mode, bit clock is provided by ISD91xx. Software can program these bits to generate bit clock frequency for the desired sample rate.
For sample rate Fs, the desired bit clock frequency is:
F(BCLK) aaa Fs x Word_width_in_bytes x 16
For example if Fs aaa 16kHz, and word width is 2-bytes (16bit) then desired bit clock frequency is 512kHz.
The bit clock frequency is given by:
F(BCLK) aaa F(I2S_CLK) / 2x(BCLKDIV+1)
Or,
BCLKDIV aaa F(I2S_CLK) / (2 x F(BCLK)) -1
So if F(I2S_CLK) aaa HCLK aaa 49.152MHz , desired F(BCLK) aaa 512kHz then BCLKDIV aaa 47
bits : 8 - 15 (8 bit)
access : read-write
I2S Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDIEN : Receive FIFO Underflow Interrupt Enable
If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
RXOVIEN : Receive FIFO Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
RXTHIEN : Receive FIFO Threshold Level Interrupt
Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
TXUDIEN : Transmit FIFO Underflow Interrupt Enable
Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
TXOVIEN : Transmit FIFO Overflow Interrupt Enable
Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
TXTHIEN : Transmit FIFO Threshold Level Interrupt Enable
Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
RZCIEN : Right Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and right channel has zero cross event
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
LZCIEN : Left Channel Zero Cross Interrupt Enable
Interrupt will occur if this bit is set to 1 and left channel has zero cross event
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable interrupt
#1 : 1
Enable interrupt
End of enumeration elements list.
I2S Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2SIF : I2S Interrupt (Read Only)
This bit is set if any enabled I2S interrupt is active.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
No I2S interrupt
#1 : 1
I2S interrupt active
End of enumeration elements list.
RXIF : I2S Receive Interrupt (Read Only)
This indicates that there is an active receive interrupt source. This could be RXOVIF, RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
No receive interrupt
#1 : 1
Receive interrupt occurred
End of enumeration elements list.
TXIF : I2S Transmit Interrupt (Read Only)
This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
No transmit interrupt
#1 : 1
Transmit interrupt occurred
End of enumeration elements list.
RIGHT : Right Channel Active (Read Only)
This bit indicates current data being transmitted/received belongs to right channel
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
Left channel
#1 : 1
Right channel
End of enumeration elements list.
RXUDIF : Receive FIFO Underflow Flag (Write '1' to clear)
This flag is set if attempt is made to read receive FIFO while it is empty.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underflow
#1 : 1
Underflow
End of enumeration elements list.
RXOVIF : Receive FIFO Overflow Flag (Write '1' to clear)
This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow
#1 : 1
Overflow
End of enumeration elements list.
RXTHIF : Receive FIFO Threshold Flag (Read Only)
When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data word(s) in FIFO is less than threshold level
#1 : 1
Data word(s) in FIFO is greater than or equal to threshold level
End of enumeration elements list.
RXFULL : Receive FIFO full (Read Only)
This bit is set when receive FIFO is full.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not full
#1 : 1
Full
End of enumeration elements list.
RXEMPTY : Receive FIFO empty (Read Only)
This is set when receive FIFO is empty.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not empty
#1 : 1
Empty
End of enumeration elements list.
TXUDIF : Transmit FIFO underflow flag (Write '1' to clear)
This flag is set if I2S controller requests data when transmit FIFO is empty.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No underflow
#1 : 1
Underflow
End of enumeration elements list.
TXOVIF : Transmit FIFO Overflow Flag (Write '1' to clear)
This flag is set if data is written to transmit FIFO when it is full.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No overflow
#1 : 1
Overflow
End of enumeration elements list.
TXTHIF : Transmit FIFO Threshold Flag (Read Only)
When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold exceeded.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data word(s) in FIFO is greater than threshold level
#1 : 1
Data word(s) in FIFO is less than or equal to threshold level
End of enumeration elements list.
TXFULL : Transmit FIFO Full (Read Only)
This bit is set when transmit FIFO is full.
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not full
#1 : 1
Full
End of enumeration elements list.
TXEMPTY : Transmit FIFO Empty (Read Only)
This is set when transmit FIFO is empty.
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
Not empty
#1 : 1
Empty
End of enumeration elements list.
TXBUSY : Transmit Busy (Read Only)
This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register.
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit shift register is empty
#1 : 1
Transmit shift register is busy
End of enumeration elements list.
RZCIF : Right channel zero cross flag (write '1' to clear, or clear RZCEN)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross
#1 : 1
Right channel zero cross is detected
End of enumeration elements list.
LZCIF : Left channel zero cross flag (write '1' to clear, or clear LZCEN)
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No zero cross detected
#1 : 1
Left channel zero cross is detected
End of enumeration elements list.
RXCNT : Receive FIFO level (Read Only)
bits : 24 - 27 (4 bit)
access : read-only
TXCNT : Transmit FIFO level (Read Only)
bits : 28 - 31 (4 bit)
access : read-only
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