CRC_CTL (CTL)

CRC_DAT (DAT)

CRC_CHECKSUM (CHECKSUM)

PKTLEN : CRC Packet Length Indicates number of bytes of CRC input to process. CRC calculation will stop once input number of bytes aaa PKTLEN+1. Maximum packet size is 512 bytes, for PKTLEN aaa 511. Writing any value to this register will flush all previous calculations and restart a new CRC calculation.
bits : 0 - 8 (9 bit)
access : read-write

MODE : CRC LSB mode Determines whether CRC Generator processes input words (32bit/4Bytes) LSB (least significant byte) first or MSB (most significant byte) first. For example if MODE aaa 1, and 0x01020304 is written to CRC_DAT, bytes will be processed in order 0x04, 0x03, 0x02, 0x01. If MODE aaa 0, then order would be 0x01, 0x02, 0x3, 0x04. Writing any value to this register will flush all previous calculations and restart a new CRC calculation.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA : CRC Input The string of bytes to perform CRC calculation on. When MODE aaa 0, CRC performs calculation byte by byte in the order DATA[31:24], DATA[23:16], DATA[15:8], DATA[7:0]. When MODE aaa 1, CRC performs calculation byte by byte in the order DATA[7:0], DATA[15:8], DATA[23:16], DATA[31:24]. If number of input bytes exceeds CRC Packet Length (CRC_CTL[8:0]+1), any additional input bytes will be ignored. The CRC generator takes four clock cycles to process the CRC input. Software must ensure that at least four clock cycles occur between writes of CRC_DAT. Compiled assembly language can be examined to ensure this requirement is met.
bits : 0 - 31 (32 bit)
access : read-write

CHECKSUM : CRC Output The result of CRC computation. The result is valid four clock cycles after last CRC_DAT input data is written to CRC generator.
bits : 0 - 15 (16 bit)
access : read-only