ANA_VMID (VMID)

ANA_LDOSEL (LDOSEL)

ANA_LDOPD (LDOPD)

ANA_MICBSEL (MICBSEL)

ANA_MICBEN (MICBEN)

ANA_MUXCTL (MUXCTL)

ANA_PGACTL (PGACTL)

ANA_SIGCTL (SIGCTL)

ANA_PGAGAIN (PGAGAIN)

ANA_CURCTL0 (CURCTL0)

ANA_TRIM (TRIM)

ANA_CAPSCTL (CAPSCTL)

ANA_CAPSCNT (CAPSCNT)

ANA_FQMMCTL (FQMMCTL)

ANA_FQMMCNT (FQMMCNT)

PULLDOWN : VMID Pulldown
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDLORES : Power Down Low (4.8kΩ) Resistance Reference
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDHIRES : Power Down High (360kΩ) Resistance Reference
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDOSEL : Select LDO Output Voltage Note that maximum I/O pad operation speed only specified for voltage >2.4V.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD : Power Down LDO When powered down no current delivered to VD33.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DISCHAR : Discharge
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VOLSEL : Select Microphone Bias Voltage MICBMODE aaa 0 0: 90% VCCA 1: 65% VCCA 2: 75% VCCA 3: 50% VCCA MICBMODE aaa 1 0: 2.4V 1: 1.7V 2: 2.0V 3: 1.3V
bits : 0 - 1 (2 bit)
access : read-write

REFSEL : Select Reference Source For MICBIAS Generator VMID provides superior noise performance for MICBIAS generation and should be used unless fixed voltage is absolutely necessary, then noise performance can be sacrificed and bandgap voltage used as reference.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MICBEN : Enable Microphone Bias Generator
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NEGINSEL : Selects Connection Of GPIOB[7:0] To PGA_INN, Negative Input Of PGA If NEGINSEL[n] aaa 1 then GPIOB[n] is connected to PGA_INN.
bits : 0 - 7 (8 bit)
access : read-write

POSINSEL : Selects Connection Of GPIOB[7,5,3,1] To PGA_INP, Positive Input Of PGA 1000b: GPIOB[7] connected to PGA_INP 0100b: GPIOB[5] connected to PGA_INP 0010b: GPIOB[3] connected to PGA_INP 0001b: GPIOB[1] connected to PGA_INP
bits : 8 - 11 (4 bit)
access : read-write

PTATCUR : Select PTAT Current I_PTAT, to PGA_INN, negative input to PGA, for temperature measurement.
bits : 12 - 12 (1 bit)
access : read-write

PGAINSEL : Select MICP/MICN To PGA Inputs
bits : 13 - 13 (1 bit)
access : read-write

MUXEN : Enable The Analog Multiplexer
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFSEL : Select Reference For Analog Path Signal path is normally referenced to VMID (VCCA/2). To use an absolute reference this can be set to VBG aaa 1.2V.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUPGA : Power Up Control For PGA Amplifier This amplifier must be powered up for signal path operation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUBOOST : Power Up Control For Boost Stage Amplifier This amplifier must be powered up for signal path operation.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BSTGAIN : Boost Stage Gain Setting
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUZCDCMP : Power Up And Enable Control For Zero Cross Detect Comparator When enabled PGA gain settings will only be updated when ADC input signal crosses zero signal threshold. To operate ZCD the ALC peripheral clock (CLK_APBCLK0.BFALCKEN) must also be enabled and BIQ_CTL.DLCOEFF aaa 1 to allow ZCD clocks to be generated.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUBUFPGA : Power Up Control For PGA Reference Buffer This block must be powered up for signal path operation.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUBUFADC : Power Up Control For ADC Reference Buffer This block must be powered up for signal path operation.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUCURB : Power Up Control For Current Bias Generation This block must be powered up for signal path operation.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PUADCOP : Power Up ADC ΣΔ Modulator This block must be powered up for ADC operation.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTEPGA : PGA Mute Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MUTEBST : Boost Stage Mute Control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GAINSET : Select The PGA Gain Setting From -12dB to 35.25dB in 0.75dB step size. 0x00 is lowest gain setting at -12dB and 0x3F is largest gain at 35.25dB.
bits : 0 - 5 (6 bit)
access : read-write

GAINREAD : Current PGA Gain Read Only. May be different from GAIN register when AGC is enabled and is controlling the PGA gain.
bits : 8 - 13 (6 bit)
access : read-write

CURSRCEN : Enable Current Source to GPIOB[x] Individually enable current source to GPIOB pins. Each GPIOB pin has a separate current source.
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VALSEL : Current Source Value Select master current for source generation
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSCTRIM : Oscillator Trim Reads current oscillator trim setting. Read Only.
bits : 0 - 7 (8 bit)
access : read-write

COARSE : COARSE Current coarse range setting of the oscillator. Read Only
bits : 8 - 15 (8 bit)
access : read-write

SUPERFINE : Superfine The superfine trim setting is an 8bit signed integer. It adjusts the master oscillator by dithering the FINE trim setting between the current setting and one setting above (values 1,127) or below (values -1, -128) the current trim setting. Each step effectively moves the frequency 1/128th of the full FINE trim step size.
bits : 16 - 23 (8 bit)
access : read-write

LOWTIME : Output Low Time Number of PCLK cycles to discharge external capacitor.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCLECNT : Number of Relaxation Cycles Peripheral performs 2^(CYCLECNT) relaxation cycles before generating interrupt.
bits : 2 - 4 (3 bit)
access : read-write

CLKMODE : Reference Clock Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKDIV : Reference Clock Divider Circuit can be used to generate a reference clock output of SDCLK/2/(CLKDIV+1) instead of a Capacitive Touch Sensing reset signal.
bits : 8 - 15 (8 bit)
access : read-write

RSTCNT : Reset Count 0: Release/Activate ANA_CAPSCNT 1: Set high to reset ANA_CAPSCNT.
bits : 29 - 29 (1 bit)
access : read-write

INTEN : Interrupt Enable
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSEN : Enable
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPSCNT : Counter Read Back Value Of Capacitive Touch Sensing Block
bits : 0 - 23 (24 bit)
access : read-only

CLKSEL : Reference Clock Source 00b: OSC16K, 01b: OSC32K (default), 1xb: I2S_WS - can be GPIOA[4,8,12] according to SYS_GPA_MFP register, configure I2S in SLAVE mode to enable.
bits : 0 - 1 (2 bit)
access : read-write

MMSTS : Measurement Done
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCLESEL : Frequency Measurement Cycles Number of reference clock periods plus one to measure target clock (PCLK). For example if reference clock is OSC32K (T is 30.5175us), set CYCLESEL to 7, then measurement period would be 30.5175*(7+1), 244.1us.
bits : 16 - 23 (8 bit)
access : read-write

FQMMEN : FQMMEN
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FQMMCNT : Frequency Measurement Count When MMSTS aaa 1 and G0 aaa 1, this is number of PCLK periods counted for frequency measurement. The frequency will be PCLK aaa FQMMCNT * Fref /(CYCLESEL+1) Hz Maximum resolution of measurement is Fref /(CYCLESEL+1)*2 Hz
bits : 0 - 15 (16 bit)
access : read-only