\n
address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Coefficient b0 In H(z) Transfer Function
(3.16 format) - 1st stage BIQ Coefficients
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFFDAT : Coefficient Data
bits : 0 - 31 (32 bit)
access : read-write
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQ Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQEN : BIQ Filter Start To Run
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BIQ filter is not processing
#1 : 1
BIQ filter is on
End of enumeration elements list.
PATHSEL : AC Path Selection For BIQ
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
used in ADC path
#1 : 1
used in DPWM path
End of enumeration elements list.
PRGCOEFF : Programming Mode Coefficient Control Bit
This bit must be turned off when BIQEN in on.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Coefficient RAM is in normal mode
#1 : 1
coefficient RAM is under programming mode
End of enumeration elements list.
DLCOEFF : Move BIQ Out Of Reset State
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BIQ filter is in reset state
#1 : 1
When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on
End of enumeration elements list.
DPWMPUSR : DPWM Path Up Sample Rate (From SRDIV Result)
This register is only used when PATHSEL is set to 1. The operating sample rate for the biquad filter will be
(DPWMPUSR+1)*HCLK/(SRDIV+1).
Default value for this register is 3.
bits : 4 - 6 (3 bit)
access : read-write
SRDIV : Sample Rate Divider
This register is used to program the operating sampling rate of the biquad filter. The sample rate is defined as
HCLK/(SRDIV+1).
Default to 3071 so the sampling rate is 16K when HCLK is 49.152MHz.
bits : 16 - 28 (13 bit)
access : read-write
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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