SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_IRCTCTL (IRCTCTL)

SYS_OSC10KTRIM (OSC10KTRIM)

SYS_OSCTRIM0 (OSCTRIM0)

SYS_OSCTRIM1 (OSCTRIM1)

SYS_OSCTRIM2 (OSCTRIM2)

SYS_XTALTRIM (XTALTRIM)

Reserved

SYS_GPSMTEN (GPSMTEN)

SYS_GPA_MFP (GPA_MFP)

SYS_GPB_MFP (GPB_MFP)

SYS_RSTSTS (RSTSTS)

SYS_WKCTL (WKCTL)

SYS_IPRST0 (IPRST0)

SYS_IPRST1 (IPRST1)

PDID : Product Identifier Chip identifier for I91200 series.
bits : 0 - 31 (32 bit)
access : read-only

REGLCTL : Protected Register Unlock Register
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ : Current oscillator frequency trim value. (based on CLK_CLKSEL0.HIRCFSEL)
bits : 0 - 9 (10 bit)
access : read-write

RANGE : 1: Low Frequency mode of oscillator active (2MHz). 0: High frequency mode (20-50MHz)
bits : 15 - 15 (1 bit)
access : read-write

TRIM : 23bit trim for LIRC.
bits : 0 - 22 (23 bit)
access : read-write

TRMCLK :
bits : 31 - 31 (1 bit)
access : read-write

TRIM : 16bit sign extended representation of 10bit trim.
bits : 0 - 15 (16 bit)
access : read-write

EN2MHZ : 1: Low Frequency mode of oscillator active (2MHz). 0: High frequency mode (20-50MHz)
bits : 31 - 31 (1 bit)
access : read-write

TRIM : 16bit sign extended representation of 10bit trim.
bits : 0 - 15 (16 bit)
access : read-write

EN2MHZ : 1: Low Frequency mode of oscillator active (2MHz). 0: High frequency mode (20-50MHz)
bits : 31 - 31 (1 bit)
access : read-write

TRIM : 16bit sign extended representation of 10bit trim.
bits : 0 - 15 (16 bit)
access : read-write

EN2MHZ : 1: Low Frequency mode of oscillator active (2MHz). 0: High frequency mode (20-50MHz)
bits : 31 - 31 (1 bit)
access : read-write

LOWPWR : 1: low power mode. 0: normal mode.
bits : 9 - 9 (1 bit)
access : read-write

SELXT : HXT select external clock 0: Disable 1: Enable
bits : 16 - 16 (1 bit)
access : read-write

XGS : HXT Gain Select
bits : 24 - 25 (2 bit)
access : read-write

SSGPAG0 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPAG0 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPAG1 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPAG1 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPAG2 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPAG2 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPAG3 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPAG3 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPBG0 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPBG0 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPBG1 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPBG1 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPBG2 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPBG2 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSGPBG3 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSSGPBG3 : this Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Dr. Each bit controls a group of four GPIO pins
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0MFP : Alternate Function Setting for PA0MFP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA1MFP : Alternate Function Setting for PA1MFP
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA2MFP : Alternate Function Setting for PA2MFP
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA3MFP : Alternate Function Setting for PA3MFP
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA4MFP : Alternate Function Setting for PA4MFP
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA5MFP : Alternate Function Setting for PA5MFP
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA6MFP : Alternate Function Setting for PA6MFP
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA7MFP : Alternate Function Setting for PA7MFP
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA8MFP : Alternate Function Setting for PA8MFP
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA9MFP : Alternate Function Setting for PA9MFP
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA10MFP : Alternate Function Setting for PA10MFP
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA11MFP : Alternate Function Setting for PA11MFP
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA12MFP : Alternate Function Setting for PA12MFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA13MFP : Alternate Function Setting for PA13MFP
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA14MFP : Alternate Function Setting for PA14MFP
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA15MFP : Alternate Function Setting for PA15MFP
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB0MFP : Alternate Function Setting for PB0MFP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB1MFP : Alternate Function Setting for PB1MFP
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB2MFP : Alternate Function Setting for PB2MFP
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB3MFP : Alternate Function Setting for PB3MFP
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB4MFP : Alternate Function Setting for PB4MFP
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB5MFP : Alternate Function Setting for PB5MFP
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB6MFP : Alternate Function Setting for PB6MFP
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB7MFP : Alternate Function Setting for PB7MFP
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB8MFP : Alternate Function Setting for PB8MFP
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB9MFP : Alternate Function Setting for PB9MFP
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB10MFP : Alternate Function Setting for PB10MFP
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB11MFP : Alternate Function Setting for PB11MFP
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB12MFP : Alternate Function Setting for PB12MFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB13MFP : Alternate Function Setting for PB13MFP
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB14MFP : Alternate Function Setting for PB14MFP
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PB15MFP : Alternate Function Setting for PB15MFP
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CORERSTF : Reset Source From CORE The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset. This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PADRF : The RSTS_PAD Flag Is If Pervious Reset Source Originates From the /RESET Pin This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : Reset Source From WDT The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. This bit is cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : Low Voltage Reset Flag The LVRF flag is set if pervious reset source originates from the LVR module. This bit is cleared by writing 1 to itself.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRF : Reset Source From MCU The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel. This bit is cleared by writing 1 to itself.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMURSTF : Reset Source From PMU The PMURSTF flag is set if the PMU. This bit is cleared by writing 1 to itself.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURF : Reset Source From CPU The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit is cleared by writing 1 to itself.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKRSTF : Wakeup Pin Reset Flag The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPDRSTF : Deep Power Down Reset Flag The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORF : Power on Reset Flag The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRST : CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles. CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. This bit is a protected bit, to program first issue the unlock sequence
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles This bit is a protected bit, to program first issue the unlock sequence
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1RST : SPI1 Controller Reset
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMRST : DPWM Speaker Driver Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIQRST : Biquad Filter Block Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SARADCRST : SAR ADC Controller Reset,
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDADCRST : SDADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0RST : I2S Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ANARST : Analog Block Control Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.