\n

GPIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

PA_MODE

PA_PIN

PA_DBEN

PA_INTTYPE

GPIO_DBCTL (DBCTL)

PA_INTEN

PA_INTSRC

PA_DINOFF

PB_MODE

PB_DINOFF

PB_DOUT

PB_DATMSK

PB_PIN

PB_DBEN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PA_DOUT

PA_DATMSK


PA_MODE

GPIO Port A Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_MODE PA_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE0 MODE1 MODE2 MODE3 MODE4 MODE5 MODE6 MODE7 MODE8 MODE9 MODE10 MODE11 MODE12 MODE13 MODE14 MODE15

MODE0 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE1 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE2 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE3 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE4 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE5 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE6 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE7 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE8 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE9 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE10 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE11 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE12 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE13 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE14 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.

MODE15 : Px I/O Pin[n] Mode Control Determine each I/O type of GPIOx pins
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO port [n] pin is in INPUT mode

#01 : 1

GPIO port [n] pin is in OUTPUT mode

#10 : 2

GPIO port [n] pin is in Open-Drain mode

#11 : 3

GPIO port [n] pin is in Quasi-bidirectional mode

End of enumeration elements list.


PA_PIN

GPIO Port A Pin Value
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PA_PIN PA_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN

PIN : Port [A/B] Pin Values The value read from each of these bit reflects the actual status of the respective GPIO pin
bits : 0 - 15 (16 bit)
access : read-only


PA_DBEN

GPIO Port A De-bounce Enable
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DBEN PA_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBEN

DBEN : Port [A/B] De-bounce Enable Control DBEN[n]used to enable the de-bounce function for each corresponding bit. For an edge triggered interrupt to be generated, input signal must be valid for two consecutive de-bounce periods. The de-bounce time is controlled by the GPIO_DBCTL register. The DBEN[n] is used for edge-trigger interrupt only it is ignored for level trigger interrupt
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

The bit[n] de-bounce function is disabled

1 : 1

The bit[n] de-bounce function is enabled

End of enumeration elements list.


PA_INTTYPE

GPIO Port A Interrupt Trigger Type
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTTYPE PA_INTTYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TYPE

TYPE : Port [A/B] Edge or Level Detection Interrupt Trigger Type TYPE[n] used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is edge triggered, edge de-bounce is controlled by the DBEN register. If the interrupt mode is level triggered, the input source is sampled each clock to generate an interrupt If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set no interrupt will occur
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

Edge triggered interrupt

1 : 1

Level triggered interrupt

End of enumeration elements list.


GPIO_DBCTL (DBCTL)

Interrupt De-bounce Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_DBCTL GPIO_DBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBCLKSEL DBCLKSRC ICLKON

DBCLKSEL : De-bounce Sampling Cycle Selection
bits : 0 - 3 (4 bit)
access : read-write

DBCLKSRC : De-bounce Counter Clock Source Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

De-bounce counter clock source is HCLK

#1 : 1

De-bounce counter clock source is the internal 16 kHz clock

End of enumeration elements list.

ICLKON : Interrupt Clock on Mode Set this bit 0 will gate the clock to the interrupt generation circuit if the GPIOx[n] interrupt is disabled.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

disable the clock if the GPIOx[n] interrupt is disabled

#1 : 1

Interrupt generation clock always active

End of enumeration elements list.


PA_INTEN

GPIO Port A Interrupt Enable
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTEN PA_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLIEN RHIEN

FLIEN : Port [A/B] Interrupt Enable by Input Falling Edge or Input Level Low FLIEN[n] is used to enable the falling/low interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level low will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from high-to-low will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

Disable GPIOx[n] for low-level or high-to-low interrupt

1 : 1

Enable GPIOx[n] for low-level or high-to-low interrupt

End of enumeration elements list.

RHIEN : Port [A/B] Interrupt Enable by Input Rising Edge or Input Level High RHIEN[n] is used to enable the rising/high interrupt for each of the corresponding GPIO pins. It also enables the pin wakeup function. If the interrupt is configured in level trigger mode, a level high will generate an interrupt. If the interrupt is configured in edge trigger mode, a state change from low-to-high will generate an interrupt. GPB.0 and GPB.1 trigger individual IRQ vectors (IRQ2/IRQ3) while remaining GPIO trigger a single interrupt vector IRQ4.
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

Disable GPIOx[n] for level-high or low-to-high interrupt

1 : 1

Enable GPIOx[n] for level-high or low-to-high interrupt

End of enumeration elements list.


PA_INTSRC

GPIO Port A Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_INTSRC PA_INTSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSRC

INTSRC : Port [A/B] Interrupt Source Flag Read :
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No interrupt from GPIOx[n]. No action

1 : 1

Indicates GPIOx[n] generated an interrupt. Clear the corresponding pending interrupt

End of enumeration elements list.


PA_DINOFF

GPIO Port A Pin Input Disable
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DINOFF PA_DINOFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DINOFF

DINOFF : GPIOx Pin[n] OFF Digital Input Path Enable
bits : 16 - 31 (16 bit)
access : read-write

Enumeration:

0 : 0

Enable IO digital input path (Default)

1 : 1

Disable IO digital input path (low leakage mode)

End of enumeration elements list.


PB_MODE

GPIO Port B Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_MODE PB_MODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_DINOFF

GPIO Port B Pin Input Disable
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DINOFF PB_DINOFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_DOUT

GPIO Port B Data Output Value
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DOUT PB_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_DATMSK

GPIO Port B Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DATMSK PB_DATMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_PIN

GPIO Port B Pin Value
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_PIN PB_PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_DBEN

GPIO Port B De-bounce Enable
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_DBEN PB_DBEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_INTTYPE

GPIO Port B Interrupt Trigger Type
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTTYPE PB_INTTYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_INTEN

GPIO Port B Interrupt Enable
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTEN PB_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PB_INTSRC

GPIO Port B Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PB_INTSRC PB_INTSRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA_DOUT

GPIO Port A Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DOUT PA_DOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUT

DOUT : Px Pin[n] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

GPIO port [A/B] Pin[n] will drive Low if the corresponding output mode bit is set

1 : 1

GPIO port [A/B] Pin[n] will drive High if the corresponding output mode bit is set

End of enumeration elements list.


PA_DATMSK

GPIO Port A Data Output Write Mask
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PA_DATMSK PA_DATMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATMSK

DATMSK : Port [A/B] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT bit[n] . When set the DATMSK bit[n] to 1 , the corresponding DOUTn bit is writing protected.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

The corresponding Px_DOUT[n] bit can be updated

1 : 1

The corresponding Px_DOUT[n] bit is read only

End of enumeration elements list.



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