PWM_CLKPSC (CLKPSC)

PWM_CMPDAT0 (CMPDAT0)

PWM_CNT0 (CNT0)

PWM_PERIOD1 (PERIOD1)

PWM_CMPDAT1 (CMPDAT1)

PWM_CNT1 (CNT1)

PWM_PERIOD2 (PERIOD2)

PWM_CMPDAT2 (CMPDAT2)

PWM_CNT2 (CNT2)

PWM_PERIOD3 (PERIOD3)

PWM_CMPDAT3 (CMPDAT3)

PWM_CNT3 (CNT3)

PWM_CLKDIV (CLKDIV)

PWM_INTEN (INTEN)

PWM_INTSTS (INTSTS)

PWM_CAPCTL01 (CAPCTL01)

PWM_CAPCTL23 (CAPCTL23)

PWM_RCAPDAT0 (RCAPDAT0)

PWM_FCAPDAT0 (FCAPDAT0)

PWM_RCAPDAT1 (RCAPDAT1)

PWM_FCAPDAT1 (FCAPDAT1)

PWM_RCAPDAT2 (RCAPDAT2)

PWM_FCAPDAT2 (FCAPDAT2)

PWM_RCAPDAT3 (RCAPDAT3)

PWM_FCAPDAT3 (FCAPDAT3)

PWM_CAPINEN (CAPINEN)

PWM_POEN (POEN)

PWM_CTL (CTL)

PWM_PERIOD0 (PERIOD0)

CLKPSC01 : Clock Pre-scaler Pair of PWM0CH0 and PWM0CH1 Clock input is divided by (CLKPSC01 + 1) This implies PWM counter 0 and 1 will also be stopped.
bits : 0 - 7 (8 bit)
access : read-write

CLKPSC23 : Clock Pre-scaler for Pair of PWM0CH2 and PWM0CH3 Clock input is divided by (CLKPSC23 + 1) This implies PWM counter 2 and 3 will also be stopped.
bits : 8 - 15 (8 bit)
access : read-write

DTCNT01 : Dead Zone Interval Register for Pair of PWM0CH0 and PWM0CH1 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write

DTCNT23 : Dead Zone Interval Register for Pair of PWM0CH2 and PWM0CH3 These 8 bits determine dead zone length. The unit time of dead zone length is that from clock selector 0.
bits : 24 - 31 (8 bit)
access : read-write

CMP : PWM Comparator Register CMP determines the PWM duty cycle. Note: Any write to CMP will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CNT : PWM Data Register Reports the current value of the 16-bit down counter.
bits : 0 - 15 (16 bit)
access : read-only

CLKDIV0 : Timer 0 Clock Source Selection Value : Input clock divided by 0 : 2 1 : 4 2 : 8 3 : 16 4 : 1
bits : 0 - 2 (3 bit)
access : read-write

CLKDIV1 : Timer 1 Clock Source Selection (Table is as CLKDIV0)
bits : 4 - 6 (3 bit)
access : read-write

CLKDIV2 : Timer 2 Clock Source Selection (Table is as CLKDIV0)
bits : 8 - 10 (3 bit)
access : read-write

CLKDIV3 : Timer 3 Clock Source Selection (Table is as CLKDIV0)
bits : 12 - 14 (3 bit)
access : read-write

PIEN0 : PWM Timer 0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN1 : PWM Timer 1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN2 : PWM Timer 2 Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIEN3 : PWM Timer 3 Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIF0 : PWM Timer 0 Interrupt Flag Flag is set by hardware when PWM0CH0 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

PIF1 : PWM Timer 1 Interrupt Flag Flag is set by hardware when PWM0CH1 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

PIF2 : PWM Timer 2 Interrupt Flag Flag is set by hardware when PWM0CH2 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-write

PIF3 : PWM Timer 3 Interrupt Flag Flag is set by hardware when PWM0CH3 down counter reaches zero, software can clear this bit by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-write

CAPINV0 : Channel 0 Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN0 : Channel 0 Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN0 : Channel 0 Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN0 : Capture Channel 0 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag
bits : 4 - 4 (1 bit)
access : read-write

CRLIF0 : PWM_RCAPDAT0 Latched Indicator Bit When input channel 0 has a rising transition, PWM_RCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLIF0 : PWM_FCAPDAT0 Latched Indicator Bit When input channel 0 has a falling transition, PWM_FCAPDAT0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 7 - 7 (1 bit)
access : read-write

CAPINV1 : Channel 1 Inverter ON/OFF
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN1 : Channel 1 Rising Latch Interrupt Enable When enabled, capture block generates an interrupt on rising edge of input.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN1 : Channel 1 Falling Latch Interrupt Enable When enabled, capture block generates an interrupt on falling edge of input.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN1 : Capture Channel 1 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Capture1 Interrupt Indication Flag
bits : 20 - 20 (1 bit)
access : read-write

CRLIF1 : PWM_RCAPDAT1 Latched Indicator Bit When input channel 1 has a rising transition, PWM_RCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLIF1 : PWM_FCAPDAT1 Latched Indicator Bit When input channel 1 has a falling transition, PWM_FCAPDAT1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 23 - 23 (1 bit)
access : read-write

CAPINV2 : Channel 2 Inverter ON/OFF
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN2 : Channel 2 Rising Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on rising edge of input.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN2 : Channel 2 Falling Latch Interrupt Enable ON/OFF When enabled, capture block generates an interrupt on falling edge of input.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN2 : Capture Channel 2 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF2 : Capture2 Interrupt Indication Flag
bits : 4 - 4 (1 bit)
access : read-write

CRLIF2 : PWM_RCAPDAT2 Latched Indicator Bit When input channel 2 has a rising transition, PWM_RCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLIF2 : PWM_FCAPDAT2 Latched Indicator Bit When input channel 2 has a falling transition, PWM_FCAPDAT2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 7 - 7 (1 bit)
access : read-write

CAPINV3 : Channel 3 Inverter ON/OFF
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRLIEN3 : Channel 3 Rising Latch Interrupt Enable When enabled, capture block generates an interrupt on rising edge of input.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFLIEN3 : Channel 3 Falling Latch Interrupt Enable When enabled, capture block generates an interrupt on falling edge of input.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN3 : Capture Channel 3 Transition Enable/Disable When enabled, Capture function latches the PMW-counter to RCAPDAT (Rising latch) and FCAPDAT (Falling latch) registers on input edge transition. When disabled, Capture function is inactive as is interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF3 : Capture3 Interrupt Indication Flag
bits : 20 - 20 (1 bit)
access : read-write

CRLIF3 : PWM_RCAPDAT3 Latched Indicator Bit When input channel 3 has a rising transition, PWM_RCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLIF3 : PWM_FCAPDAT3 Latched Indicator Bit When input channel 3 has a falling transition, PWM_FCAPDAT3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a zero to it.
bits : 23 - 23 (1 bit)
access : read-write

RCAPDAT : Capture Rising Latch Register In Capture mode, this register is latched with the value of the PWM counter on a rising edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

FCAPDAT : Capture Falling Latch Register In Capture mode, this register is latched with the value of the PWM counter on a falling edge of the input signal.
bits : 0 - 15 (16 bit)
access : read-only

CAPINEN : Capture Input Enable Register 0 : OFF (GPA[13:12], GPB[15:14] pin input disconnected from Capture block) 1 : ON (GPA[13:12] , GPB[15:14] pin, if in PWM alternative function, will be configured as an input and fed to capture function) CAPINEN[3:0] Bit [3][2][1][0] Bit xxx1 : Capture channel 0 is from GPA [12] Bit xx1x : Capture channel 1 is from GPA [13] Bit x1xx : Capture channel 2 is from GPB [14] Bit 1xxx : Capture channel 3 is from GPB [15]
bits : 0 - 3 (4 bit)
access : read-write

POEN0 : PWM0CH0 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN1 : PWM0CH1 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN2 : PWM0CH2 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POEN3 : PWM0CH3 Output Enable Register Note: The corresponding GPIO pin also must be switched to PWM function (refer to SYS_GPA_MFP)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN0 : PWM-timer 0 Enable/Disable Start Run
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV0 : PWM-timer 0 Output Inverter ON/OFF
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE0 : PWM-timer 0 Auto-reload/One-shot Mode Note: A rising transition of this bit will cause PWM_PERIOD0 and PWM_CMPDAT0 to be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEN01 : Dead-zone 01 Generator Enable/Disable Pair of PWM0CH0 and PWM0CH1 Note: When Dead-Zone Generator is enabled, the pair of PWM0CH0 and PWM0CH1 become a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTEN23 : Dead-zone 23 Generator Enable/Disable Pair of PWM0CH2 and PWM0CH3 Note: When Dead-Zone Generator is enabled, the pair of PWM0CH2 and PWM0CH3 become a complementary pair.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN1 : PWM-timer 1 Enable/Disable Start Run
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV1 : PWM-timer 1 Output Inverter ON/OFF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE1 : PWM-timer 1 Auto-reload/One-shot Mode Note: A rising transition of this bit will cause PWM_PERIOD1 and PWM_CMPDAT1 to be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN2 : PWM-timer 2 Enable/Disable Start Run
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV2 : PWM-timer 2 Output Inverter ON/OFF
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE2 : PWM-timer 2 Auto-reload/One-shot Mode Note: A rising transition of this bit will cause PWM_PERIOD2 and PWM_CMPDAT2 to be cleared.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN3 : PWM-timer 3 Enable/Disable Start Run
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINV3 : PWM-timer 3 Output Inverter ON/OFF
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTMODE3 : PWM-timer 3 Auto-reload/One-shot Mode Note: A rising transition of this bit will cause PWM_PERIOD3 and PWM_CMPDAT3 to be cleared.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PERIOD : PWM Counter/Timer Reload Value PERIOD determines the PWM period. Note: Any write to PERIOD will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write