I2S_CTL (CTL)

I2S_TX (TX)

I2S_RX (RX)

I2S_CLK (CLK)

I2S_IEN (IEN)

I2S_STATUS (STATUS)

I2SEN : Enable I2S Controller
bits : 0 - 0 (1 bit)
access : read-write

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TXEN : Transmit Enable
bits : 1 - 1 (1 bit)
access : read-write

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RXEN : Receive Enable
bits : 2 - 2 (1 bit)
access : read-write

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MUTE : Transmit Mute Enable
bits : 3 - 3 (1 bit)
access : read-write

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WDWIDTH : Word Width This parameter sets the word width of audio data. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.
bits : 4 - 5 (2 bit)
access : read-write

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MONO : Monaural Data This parameter sets whether mono or stereo data is processed. See Figure 581 FIFO contents for various I2S modes for details of how data is formatted in transmit and receive FIFO.
bits : 6 - 6 (1 bit)
access : read-write

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FORMAT : Data Format
bits : 7 - 7 (1 bit)
access : read-write

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SLAVE : Slave Mode I2S can operate as a master or slave. For master mode, I2S_BCLK and I2S_FS pins are outputs and send bit clock and frame sync from I91200. In slave mode, I2S_BCLK and I2S_FS pins are inputs and bit clock and frame sync are received from external audio device.
bits : 8 - 8 (1 bit)
access : read-write

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TXTH : Transmit FIFO Threshold Level If remaining data words in transmit FIFO less than or equal to the threshold level then TXTHI flag is set.
bits : 9 - 11 (3 bit)
access : read-write

RXTH : Receive FIFO Threshold Level When received data word(s) in buffer is equal or higher than threshold level then RXTHI flag is set.
bits : 12 - 14 (3 bit)
access : read-write

MCLKEN : Master Clock Enable The I91200can generate a master clock signal to an external audio CODEC to synchronize the audio devices. If audio devices are not synchronous, then data will be periodically corrupted. Software needs to implement a way to drop/repeat or interpolate samples in a jitter buffer if devices are not synchronized. The master clock frequency is determined by the I2S_CLKDIV.MCLKDIV[2:0] register.
bits : 15 - 15 (1 bit)
access : read-write

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RZCEN : Right Channel Zero Cross Detect Enable If this bit is set to 1, when right channel data sign bit changes, or data bits are all zero, the RZCIF flag in I2S_STATUS register will be set to 1.
bits : 16 - 16 (1 bit)
access : read-write

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LZCEN : Left Channel Zero Cross Detect Enable If this bit is set to 1, when left channel data sign bit changes, or data bits are all zero, the LZCIF flag in I2S_STATUS register will be set to 1.
bits : 17 - 17 (1 bit)
access : read-write

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TXCLR : Clear Transmit FIFO Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.TXCNT[3:0] returns to zero and transmit FIFO becomes empty. Data in transmit FIFO is not changed. This bit is cleared by hardware automatically when clear operation complete.
bits : 18 - 18 (1 bit)
access : read-write

RXCLR : Clear Receive FIFO Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and I2S_STATUS.RXCNT[3:0] returns to zero and receive FIFO becomes empty. This bit is cleared by hardware automatically when clear operation complete.
bits : 19 - 19 (1 bit)
access : read-write

TXPDMAEN : Enable Transmit DMA When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
bits : 20 - 20 (1 bit)
access : read-write

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RXPDMAEN : Enable Receive DMA When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
bits : 21 - 21 (1 bit)
access : read-write

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TX : Transmit FIFO Register (Write Only) A write to this register pushes data onto the transmit FIFO. The transmit FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.TXCNT.
bits : 0 - 31 (32 bit)
access : write-only

RX : Receive FIFO Register (Read Only) A read of this register will pop data from the receive FIFO. The receive FIFO is eight words deep. The number of words currently in the FIFO can be determined by reading I2S_STATUS.RXCNT.
bits : 0 - 31 (32 bit)
access : read-only

MCLKDIV : Master Clock Divider I91200can generate a master clock to synchronously drive an external audio device. If MCLKDIV is set to 0, MCLK is the same as I2S_CLKDIV clock input, otherwise MCLK frequency is given by:
bits : 0 - 2 (3 bit)
access : read-write

BCLKDIV : Bit Clock Divider If I2S operates in master mode, bit clock is provided by I91200. Software can program these bits to generate bit clock frequency for the desired sample rate. For sample rate Fs, the desired bit clock frequency is:
bits : 8 - 15 (8 bit)
access : read-write

RXUDIEN : Receive FIFO Underflow Interrupt Enable If software read receive FIFO when it is empty then RXUDIF flag in I2SSTATUS register is set to 1.
bits : 0 - 0 (1 bit)
access : read-write

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RXOVIEN : Receive FIFO Overflow Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

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RXTHIEN : Receive FIFO Threshold Level Interrupt Interrupt occurs if this bit is set to 1 and data words in receive FIFO is greater than or equal to RXTH[2:0].
bits : 2 - 2 (1 bit)
access : read-write

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TXUDIEN : Transmit FIFO Underflow Interrupt Enable Interrupt occur if this bit is set to 1 and transmit FIFO underflow flag is set to 1.
bits : 8 - 8 (1 bit)
access : read-write

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TXOVIEN : Transmit FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmit FIFO overflow flag is set to 1
bits : 9 - 9 (1 bit)
access : read-write

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TXTHIEN : Transmit FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH[2:0].
bits : 10 - 10 (1 bit)
access : read-write

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RZCIEN : Right Channel Zero Cross Interrupt Enable Interrupt will occur if this bit is set to 1 and right channel has zero cross event
bits : 11 - 11 (1 bit)
access : read-write

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LZCIEN : Left Channel Zero Cross Interrupt Enable Interrupt will occur if this bit is set to 1 and left channel has zero cross event
bits : 12 - 12 (1 bit)
access : read-write

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I2SIF : I2S Interrupt (Read Only) This bit is set if any enabled I2S interrupt is active.
bits : 0 - 0 (1 bit)
access : read-only

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RXIF : I2S Receive Interrupt (Read Only) This indicates that there is an active receive interrupt source. This could be RXOVIF, RXUDIF or RXTHIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
bits : 1 - 1 (1 bit)
access : read-only

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TXIF : I2S Transmit Interrupt (Read Only) This indicates that there is an active transmit interrupt source. This could be TXOVIF, TXUDIF, TXTHIF, LZCIF or RZCIF if corresponding interrupt enable bits are active. To clear interrupt the corresponding source(s) must be cleared.
bits : 2 - 2 (1 bit)
access : read-only

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RIGHT : Right Channel Active (Read Only) This bit indicates current data being transmitted/received belongs to right channel
bits : 3 - 3 (1 bit)
access : read-only

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RXUDIF : Receive FIFO Underflow Flag (Write '1' to Clear) This flag is set if attempt is made to read receive FIFO while it is empty.
bits : 8 - 8 (1 bit)
access : read-write

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RXOVIF : Receive FIFO Overflow Flag (Write '1' to Clear) This flag is set if I2S controller writes to receive FIFO when it is full. Audio data is lost.
bits : 9 - 9 (1 bit)
access : read-write

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RXTHIF : Receive FIFO Threshold Flag (Read Only) When data word(s) in receive FIFO is greater than or equal to threshold value set in RXTH[2:0] the RXTHIF bit becomes to 1. It remains set until receive FIFO level is less than RXTH[2:0]. It is cleared by reading I2S_RX until threshold satisfied.
bits : 10 - 10 (1 bit)
access : read-only

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RXFULL : Receive FIFO Full (Read Only) This bit is set when receive FIFO is full.
bits : 11 - 11 (1 bit)
access : read-only

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RXEMPTY : Receive FIFO Empty (Read Only) This is set when receive FIFO is empty.
bits : 12 - 12 (1 bit)
access : read-only

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TXUDIF : Transmit FIFO Underflow Flag (Write '1' to Clear) This flag is set if I2S controller requests data when transmit FIFO is empty.
bits : 16 - 16 (1 bit)
access : read-write

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TXOVIF : Transmit FIFO Overflow Flag (Write '1' to Clear) This flag is set if data is written to transmit FIFO when it is full.
bits : 17 - 17 (1 bit)
access : read-write

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TXTHIF : Transmit FIFO Threshold Flag (Read Only) When data word(s) in transmit FIFO is less than or equal to the threshold value set in TXTH[2:0] the TXTHIF bit becomes to 1. It remains set until transmit FIFO level is greater than TXTH[2:0]. Cleared by writing to I2S_TX register until threshold exceeded.
bits : 18 - 18 (1 bit)
access : read-only

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TXFULL : Transmit FIFO Full (Read Only) This bit is set when transmit FIFO is full.
bits : 19 - 19 (1 bit)
access : read-only

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TXEMPTY : Transmit FIFO Empty (Read Only) This is set when transmit FIFO is empty.
bits : 20 - 20 (1 bit)
access : read-only

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TXBUSY : Transmit Busy (Read Only) This bit is cleared when all data in transmit FIFO and Tx shift register is shifted out. It is set when first data is loaded to Tx shift register.
bits : 21 - 21 (1 bit)
access : read-only

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RZCIF : Right Channel Zero Cross Flag (Write '1' to Clear, or Clear RZCEN)
bits : 22 - 22 (1 bit)
access : read-write

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LZCIF : Left Channel Zero Cross Flag (Write '1' to Clear, or Clear LZCEN)
bits : 23 - 23 (1 bit)
access : read-write

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RXCNT : Receive FIFO Level (Read Only)
bits : 24 - 27 (4 bit)
access : read-only

TXCNT : Transmit FIFO Level (Read Only)
bits : 28 - 31 (4 bit)
access : read-only