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PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

PDMA_GCTL

PDMA_SVCSEL0

PDMA_SVCSEL1

PDMA_GINTSTS


PDMA_GCTL

PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCTL PDMA_GCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWRST CH0CKEN CH1CKEN CH2CKEN CH3CKEN

SWRST : PDMA Software Reset Note: This bit can reset all channels (global reset).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writing 0 to this bit has no effect

#1 : 1

Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles

End of enumeration elements list.

CH0CKEN : PDMA Controller Channel 0 Clock Enable Control 1: Enable Channel 0 clock. 0: Disable Channel 0 clock.
bits : 8 - 8 (1 bit)
access : read-write

CH1CKEN : PDMA Controller Channel 1 Clock Enable Control 1: Enable Channel 1 clock. 0: Disable Channel 1 clock.
bits : 9 - 9 (1 bit)
access : read-write

CH2CKEN : PDMA Controller Channel 2 Clock Enable Control 1: Enable Channel 2 clock. 0: Disable Channel 2 clock.
bits : 10 - 10 (1 bit)
access : read-write

CH3CKEN : PDMA Controller Channel 3 Clock Enable Control 1: Enable Channel 3 clock. 0: Disable Channel 3 clock.
bits : 11 - 11 (1 bit)
access : read-write


PDMA_SVCSEL0

PDMA Service Selection Control Register 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SVCSEL0 PDMA_SVCSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0RXSEL SPI0TXSEL SDADCRXSEL DPWMTXSEL UART0RXSEL UART0XSEL I2SRXSEL I2STXSEL

SPI0RXSEL : PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
bits : 0 - 3 (4 bit)
access : read-write

SPI0TXSEL : PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
bits : 4 - 7 (4 bit)
access : read-write

SDADCRXSEL : PDMA SDADC Receive Selection This field defines which PDMA channel is connected to SDADC peripheral receive (PDMA source) request.
bits : 8 - 11 (4 bit)
access : read-write

DPWMTXSEL : PDMA DPWM Transmit Selection This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
bits : 12 - 15 (4 bit)
access : read-write

UART0RXSEL : PDMA UART0 Receive Selection This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request.
bits : 16 - 19 (4 bit)
access : read-write

UART0XSEL : PDMA UART0 Transmit Selection This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request.
bits : 20 - 23 (4 bit)
access : read-write

I2SRXSEL : PDMA I2S Receive Selection This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request.
bits : 24 - 27 (4 bit)
access : read-write

I2STXSEL : PDMA I2S Transmit Selection This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request.
bits : 28 - 31 (4 bit)
access : read-write


PDMA_SVCSEL1

PDMA Service Selection Control Register 1
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_SVCSEL1 PDMA_SVCSEL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART1RXSEL UART1XSEL SPI1RXSEL SPI1TXSEL SARADCRXSEL

UART1RXSEL : PDMA UART1 Receive Selection This field defines which PDMA channel is connected to UART1 peripheral receive (PDMA source) request.
bits : 0 - 3 (4 bit)
access : read-write

UART1XSEL : PDMA UART1 Transmit Selection This field defines which PDMA channel is connected to UART1 peripheral transmit (PDMA destination) request.
bits : 4 - 7 (4 bit)
access : read-write

SPI1RXSEL : PDMA SPI1 Receive Selection This field defines which PDMA channel is connected to SPI1 peripheral receive (PDMA source) request.
bits : 8 - 11 (4 bit)
access : read-write

SPI1TXSEL : PDMA SPI1 Transmit Selection This field defines which PDMA channel is connected to SPI1 peripheral transmit (PDMA destination) request.
bits : 12 - 15 (4 bit)
access : read-write

SARADCRXSEL : PDMA SARADC Receive Selection This field defines which PDMA channel is connected to SARADC peripheral receive (PDMA source) request.
bits : 16 - 19 (4 bit)
access : read-write


PDMA_GINTSTS

PDMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_GINTSTS PDMA_GINTSTS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0INTSTS CH1INTSTS CH2INTSTS CH3INTSTS

CH0INTSTS : Interrupt Pin Status of Channel 0 (Read Only) This bit is the interrupt pin status of PDMA channel 0.
bits : 0 - 0 (1 bit)
access : read-only

CH1INTSTS : Interrupt Pin Status of Channel 1 (Read Only) This bit is the interrupt pin status of PDMA channel 1.
bits : 1 - 1 (1 bit)
access : read-only

CH2INTSTS : Interrupt Pin Status of Channel 2 (Read Only) This bit is the interrupt pin status of PDMA channel 2.
bits : 2 - 2 (1 bit)
access : read-only

CH3INTSTS : Interrupt Pin Status of Channel 3 (Read Only) This bit is the interrupt pin status of PDMA channel 3.
bits : 3 - 3 (1 bit)
access : read-only



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