Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
SD ADC FIFO Data Read Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : Delta-Sigma ADC DATA FIFO Read
A read of this register will read data from the audio FIFO and increment the read pointer. A read past empty will repeat the last data. Can be used with SDADC_FIFOSTS.THIF to determine if valid data is present in FIFO.
bits : 0 - 15 (16 bit)
access : read-only
SD ADC FIFO Status Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
THIF : ADC FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is less than to the setting value of FIFOTH
#1 : 1
The valid data count within the SDADC FIFO buffer is larger than or equal the setting value of FIFOTH
End of enumeration elements list.
POINTER : SDADC FIFO Pointer (Read Only)
The FULL bit and POINTER[3:0] indicates the field that the valid data count within the SDADC FIFO buffer.
The Maximum value shown in POINTER is 15. When the using level of SDADC FIFO Buffer equal to 16, The FULL bit is set to 1.
bits : 4 - 7 (4 bit)
access : read-only
BISTEN : BIST Enable
Internal use
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SDADC FIFO BIST testing
#1 : 1
Enable SDADC FIFO BIST testing SDADC FIFO can be testing by Cortex-M0
End of enumeration elements list.
SD ADC PDMA Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMAEN : Enable SDADC PDMA Receive Channel
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SDADC PDMA
#1 : 1
Enable SDADC PDMA
End of enumeration elements list.
SD ADC Comparator 0 Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function interrupt
#1 : 1
Enable compare function interrupt
End of enumeration elements list.
CMPCOND : Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition that result is less than CMPD
#1 : 1
Set the compare condition that result is greater or equal to CMPD
End of enumeration elements list.
CMPF : Compare Flag
When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.
bits : 3 - 3 (1 bit)
access : read-write
CMPMATCNT : Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 4 - 7 (4 bit)
access : read-write
CMPD : Comparison Data
23 bit value to compare to FIFO output word.
bits : 8 - 30 (23 bit)
access : read-write
CMPOEN : Compare Match output FIFO zero
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO data keep original one
#1 : 1
compare match then FIFO out zero
End of enumeration elements list.
SD ADC Comparator 1 Control Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPIE : Compare Interrupt Enable
If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable compare function interrupt
#1 : 1
Enable compare function interrupt
End of enumeration elements list.
CMPCOND : Compare Condition
Note: When the internal counter reaches the value (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition that result is less than CMPD
#1 : 1
Set the compare condition that result is greater or equal to CMPD
End of enumeration elements list.
CMPF : Compare Flag
When the conversion result meets condition in CMPCOND and CMPMATCNT this bit is set to 1. It is cleared by writing 1 to self.
bits : 3 - 3 (1 bit)
access : read-write
CMPMATCNT : Compare Match Count
When the A/D FIFO result matches the compare condition defined by CMPCOND, the internal match counter will increase by 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 4 - 7 (4 bit)
access : read-write
CMPD : Comparison Data
23 bit value to compare to FIFO output word.
bits : 8 - 30 (23 bit)
access : read-write
CMPOEN : Compare Match output FIFO zero
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO data keep original one
#1 : 1
compare match then FIFO out zero
End of enumeration elements list.
Sigma Delta Analog Block Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD : SDADC Power Down
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SDADC power on
#1 : 1
SDADC power off
End of enumeration elements list.
BIAS : SDADC Bias Current Selection
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
1
#01 : 1
0.75
#10 : 2
0.5
#11 : 3
1.25
End of enumeration elements list.
VREF : SDADC Chopper in Reference Buffer
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper off
#1 : 1
chopper on
End of enumeration elements list.
PGA_PU : Power up PGA
0—disable
1—enable
bits : 4 - 4 (1 bit)
access : read-write
PGA_MUTE : Mute control signal
0—disable
1—enable
bits : 5 - 5 (1 bit)
access : read-write
PGA_MODE : PGA mode selection
bits : 6 - 8 (3 bit)
access : read-write
Enumeration:
0 : 0
Disable
1 : 1
Enable
End of enumeration elements list.
PGA_IBCTR : Trim PGA Current
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0 : 0
default
End of enumeration elements list.
PGA_IBLOOP : Trim PGA current
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#1 : 1
default
End of enumeration elements list.
PGA_GAIN :
bits : 13 - 13 (1 bit)
access : read-write
PGA_DISCH : Charge inputs selected by PGA_ACDC[1:0] to VREF
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PGA_CMLCK : Common mode Threshold lock adjust enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable
#1 : 1
Disable
End of enumeration elements list.
PGA_CMLCKADJ :
bits : 16 - 17 (2 bit)
access : read-write
PGA_CLASSA : Enable Class A mode of operation
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Class AB
#1 : 1
Class A (default)
End of enumeration elements list.
PGA_TRIMOBC : Trim current in output driver
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable (default)
End of enumeration elements list.
PGA_HZMODE : Select input impedance
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
12k Ohm input impedance
#1 : 1
500k Ohm input impedance (default)
End of enumeration elements list.
PGA_ADCDC :
bits : 21 - 22 (2 bit)
access : read-write
Enumeration:
#00 : 0
Default
End of enumeration elements list.
CHOPF : SDADC Chopper Frequency in fixed chop mode
bits : 23 - 24 (2 bit)
access : read-write
Enumeration:
#00 : 0
Fs/2 (default)
#01 : 1
Fs/4
#10 : 2
Fs/8
#11 : 3
Fs/16
End of enumeration elements list.
CHOPCLKPH : SDADC Chopper Clock phase selection
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper transition after falling edge of ADC_CLK (default)
#1 : 1
chopper transition after rising edge of ADC_CLK
End of enumeration elements list.
CHOPFIX : SDADC Chopper Fixed Frequency
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
dither chopper frequency (default)
#1 : 1
choose fixed frequency
End of enumeration elements list.
CHOPORD : SDADC Chopper Order
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
1st order dithering of chopper frequency (default)
#1 : 1
2nd order dithering of chopper frequency
End of enumeration elements list.
CHOPPH : SDADC chopper phase
When chopper is off:
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
chopper switches in default state
#1 : 1
invert chopper switches
End of enumeration elements list.
CHOPEN : SDADC chopper enable
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable (default)
#1 : 1
enable
End of enumeration elements list.
AUDIOPATHSEL : Audio Path Selection, Connect SDADC input to
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
PGA (default)
#01 : 1
MICN and MICP pins (bypass PGA)
#10 : 2
Reserved
#11 : 3
Reserved
End of enumeration elements list.
SD ADC Enable Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDADCEN : SDADC Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and ADC is reset including FIFO pointers
#1 : 1
ADC Conversion enabled
End of enumeration elements list.
DINEDGE : ADC data input clock edge selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock negetive edge latch
#1 : 1
ADC clock positive edge latch
End of enumeration elements list.
DINBYPS : ADC data input bypass (internal debug)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal mode
#1 : 1
analog 5bits to FIFO for testing
End of enumeration elements list.
SD ADC Clock Divider Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : SD_CLK Clock Divider
SDADC internal clock divider. CLKDIV should be set to give a SD_CLK frequency in the range of 1.024-6.144MHz. (Refer to 7.1.4.2.)
CLKDIV must be greater than and equal 2.
bits : 0 - 7 (8 bit)
access : read-write
SD ADC Control Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSRATE : Down Sampling Ratio
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
reserved
1 : 1
down sample X 16
2 : 2
down sample X 32
3 : 3
down sample X 64
End of enumeration elements list.
FIFOBITS : FIFO Data Bits Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : 0
32 bits
1 : 1
16 bits
2 : 2
8 bits
3 : 3
24 bits
End of enumeration elements list.
FIFOTH : FIFO Threshold:
Determines at what level the ADC FIFO will generate a interrupt.
Interrupt will be generated when number of words present in ADC FIFO is >
FIFOTH.
bits : 4 - 6 (3 bit)
access : read-write
FIFOTHIE : FIFO Threshold Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable interrupt whenever FIFO level exceeds that set in FIFOTH
#1 : 1
enable interrupt whenever FIFO level exceeds that set in FIFOTH
End of enumeration elements list.
DMICEN : Digital MIC Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
keep SDADC function
#1 : 1
turn digital MIC function input from GPIO
End of enumeration elements list.
ReservedBSRATE : Down Sampling for BS
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
down sample 2000 for SPS384
#01 : 1
down sampel 4000(reserved)
#10 : 2
down sample 8000(reserved)
#11 : 3
down sample 16000 for SPS9.6,SPS19.2,SPS38.4 and SPS76.8Reserved
End of enumeration elements list.
RATESEL : Sample Rate Selection
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
choose DSRATE for SDADC
#1 : 1
choose BSRATE for BS
End of enumeration elements list.
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