Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
DPWM Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIFOWIDTH : DPWM FIFO DATA WIDTH SELETION From PDMA
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PDMA MSB 24bits PWDATA[31:8]
#01 : 1
PDMA 16 bits PWDATA[15:0]
#10 : 2
PDMA 8bits PWDATA[7:0]
#11 : 3
PDMA 24bits PWDATA[23:0]
End of enumeration elements list.
DEADTIME : DPWM Driver DEADTIME Control.
Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
bits : 3 - 3 (1 bit)
access : read-write
DPWMEN : DPWM Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DPWM
#1 : 1
Enable DPWM
End of enumeration elements list.
DWPMDRVEN : DPWM Driver Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DPWM Driver
#1 : 1
Enable DPWM Diver
End of enumeration elements list.
ReservedMUTETM : ReservedDPWM MUTE Waite Time
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
mute afer 2^13 DPWM CLOCK cycle at MUTEEN = 1
#01 : 1
mute afer 2^14 DPWM CLOCK cycle at MUTEEN = 1
#10 : 2
mute afer 2^15 DPWM CLOCK cycle at MUTEEN = 1
#11 : 3
mute afer 2^16 DPWM CLOCK cycle at MUTEEN = 1
End of enumeration elements list.
ReservedMUTEEN : ReservedDPWM NOSIE REMOVER Enable (rev C still has problem)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
turn off noise remover function
#1 : 1
turn on remover function
End of enumeration elements list.
RXTHIE : DPWM FIFO Threshold Interrupt
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
DPWM FIFO threshold interrupt Disabled
#1 : 1
DPWM FIFO threshold interrupt Enabled
End of enumeration elements list.
RXTH : DPWM FIFO Threshold
If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHIF bit will set to 1, else the RXTHIF bit will be cleared to 0.
bits : 12 - 15 (4 bit)
access : read-write
DPWM Zero Order Hold Division Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZOHDIV : DPWM Zero Order Hold, Down-sampling Divisor
The input sample rate of the DPWM is set by DPWM_CLK frequency and the divisor set in this register by the following formula:
Default is 6, which gives a sample rate of 16kHz up-sample 256 for a 24.576MHz DPWM_CLK and BIQ_CTL.DPWMPUSR is 4.
ZOH_DIV must be greater than 2
bits : 0 - 7 (8 bit)
access : read-write
DPWM DATA FIFO Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not full
#1 : 1
FIFO is full
End of enumeration elements list.
EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
FIFO is not empty
#1 : 1
FIFO is empty
End of enumeration elements list.
RXTHIF : DPWM FIFO Threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the DPWM FIFO buffer is larger than the setting value of RXTH
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of RXTH
End of enumeration elements list.
FIFOPTR : DPWM FIFO Pointer (Read Only)
The FULL bit and FIFOPOINTER indicates the field that the valid data count within the DPWM FIFO buffer.
The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
bits : 4 - 7 (4 bit)
access : read-only
BISTEN : BIST Enable
DPWM FIFO can be testing by Cortex-M0
Internal use
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
disable DPWM FIFO BIST testing
#1 : 1
enable DPWM FIFO BIST testing
End of enumeration elements list.
DPWM PDMA Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMAEN : Enable DPWM DMA Interface
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA. No requests will be made to PDMA controller
#1 : 1
Enable PDMA. Block will request data from PDMA controller whenever FIFO is not empty
End of enumeration elements list.
DPWM DATA FIFO Input
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INDATA : DPWM FIFO Audio Data Input
A write to this register pushes data onto the DPWM FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
bits : 0 - 31 (32 bit)
access : write-only
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