Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
CSCAN Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL : CSCAN Select
In single mode selects the channel (GPIOB[15:0]) to perform measurement on.
bits : 0 - 15 (16 bit)
access : read-write
CURRENT : CSCAN Oscillator current
Controls the analog bais current of the capacitive relaxation oscillator.
0:300nA 1:450nA 2:600nA 3:1200nA
bits : 16 - 17 (2 bit)
access : read-write
ReservedBIAS : CSCAN Comparator bias current
Controls the bais current of relaxation comparators. Suggest default 0. Can select lower for marginal power savings and less accuracy.
0:Normal 1:Half 3:Quarter
Keep with 0
bits : 18 - 19 (2 bit)
access : read-write
INT_EN : CSCAN Enable Interrupt
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt disabled
#1 : 1
Interrupt enabled
End of enumeration elements list.
SLOW_CLK : CSCAN Slow Clock
**Notes:
In low speed mode, for CYCLE_CNT <5, the minimum frequency of oscillation of a CAPSENSE GPIO must be > Fclk/2. Where Fclk is the frequency of LXT or LIRC depending which is selected as reference.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timebase clock is HIRC
#1 : 1
Timebase clock is LIRC (XTAL32K_EN = 0) or XTAL (XTAL32K_EN = 1)
End of enumeration elements list.
MODE0 : CSCAN Mode0
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single shot Capacitive sense
#1 : 1
Scans each channel set in SCAN_MASK and stores in RAM
End of enumeration elements list.
MODE1 : CSCAN Mode1
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt when scan finished
#1 : 1
Interrupt when DUR_CNT delay occurs
End of enumeration elements list.
DUR_CNT : CSCAN Duration Count
This counter is used to set a wakeup time after a capacitive sensing scan is complete. It is in units of low frewquency clock period (either LXT or LIRC clock) and gives delay of 160, 320, 480,640, 800, 960, 1120, 1280, 1440,1600, 1920, 2240, 2560, 2880,3200 3840 periods for settings 0,..,15.
bits : 24 - 27 (4 bit)
access : read-write
EN : CSCAN Enable
Write 1 to start. Reset by hardware when operation finished.
bits : 30 - 30 (1 bit)
access : read-write
PD : Power Down
0: Enable analog circuit
1: Power down analog circuit and block.
bits : 31 - 31 (1 bit)
access : read-write
CSCAN Analog GPIO Function Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AGPIO : CSCAN AGPIO
If bit set to 1 then corresponding GPIOB[n] is forced to an analog mode where digital input, output and pullup is disabled. Can be used to set pad into analog mode for CapSensing, SAR ADC and OPAMP functions.
bits : 0 - 15 (16 bit)
access : read-write
Operational Amplifier Control Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A0EN : OPA0 Enable or Disable Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0OEN : OPA0 Output Enable or Disable Control Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0NS : A0N Pin to OPA0 Inverting Input Control Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
no connection
#1 : 1
from A0N pin
End of enumeration elements list.
A0PS : A0P Pin to OPA0 Non-inverting Input Control Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
no connection
#1 : 1
from A0P pin
End of enumeration elements list.
A0PSEL : OPA0 Non-inverting Input Selection Bit
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
no connection
#01 : 1
from VH1 (0.9×VDDA)
#10 : 2
from VM (0.5×VDDA)
#11 : 3
: from VL1 (0.1×VDDA)
End of enumeration elements list.
A0O2N : OPA0 Output to OPA0 Inverting Input Control Bit
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0X : Operational amplifier 0 output positive logic This bit is read only
bits : 7 - 7 (1 bit)
access : read-write
A1EN : OPA1 Enable or Disable Control Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A1OEN : OPA1 Output Enable or Disable Control Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A1NS : A1N Pin to OPA1 Inverting Input Control Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
no connection
#1 : 1
from A0N pin
End of enumeration elements list.
A1PS : A1P Pin to OPA1 Non-inverting Input Control Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
no connection
#1 : 1
from A0P pin
End of enumeration elements list.
A1PSEL : OPA1 Non-inverting Input Selection Bit
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
no connection
#01 : 1
from VH1 (0.9×VDDA)
#10 : 2
from VM (0.5×VDDA )
#11 : 3
: from VL1 (0.1×VDDA)
End of enumeration elements list.
A102N : OPA1 Output to OPA1 Inverting Input Control Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A1X : Operational amplifier 1 output positive logic This bit is read only
bits : 15 - 15 (1 bit)
access : read-write
PGA : OPA1 Gain Control Bits
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
1
#001 : 1
8
#010 : 2
16
#011 : 3
24
#100 : 4
32
#101 : 5
40
#110 : 6
48
#111 : 7
56
End of enumeration elements list.
PGAEN : OPA1 PGA Gain Enable Control Bits
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
Enable
End of enumeration elements list.
VREFEN : Enable OPA and Comparator Reference Voltage Generator
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0O2A1P : OPA0 Output to OPA1 Non-inverting Input Control Bit
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0O2A1N : OPA0 Output to OPA0 Inverting Input Control Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
LPWREN : Enable Opamps in STOP/SPD modes
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A0O2CIN : OPA0 output to comparator input control bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
A1O2CIN : OPA1 output to comparator input control bit
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
Comparator Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1EN : Comparator 1 enable or disable control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
C1NSEL : Comparator 1 inverting input control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
from VH0
#1 : 1
from C1N pin
End of enumeration elements list.
C1OUTEN : Comparator 1 output pin control bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
C1INTEN : Comparator 1 interrupt control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
CMP_INT : Comparator Interrupt.
Set by harddware.
Write 1 to clear.
bits : 4 - 4 (1 bit)
access : read-write
CNPSEL : Comparator non-inverting input control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
from OPA output
#1 : 1
from CNP pin
End of enumeration elements list.
CMP2EN : Comparator 2 enable or disable control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
C2PSEL : Comparator 2 inverting input control
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
from VL0
#1 : 1
from C2P pin
End of enumeration elements list.
C2OUTEN : Comparator 2 output pin control bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
C2INTEN : Comparator 2 interrupt control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable
End of enumeration elements list.
CMPES : Interrupt edge control bits
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
disable
#01 : 1
rising edge trigger
#10 : 2
falling edge trigger
#11 : 3
dual edge trigger
End of enumeration elements list.
C1OUT : Comparator 1 Output.
Real time readback of comparator 1.
bits : 16 - 16 (1 bit)
access : read-write
C2OUT : Comparator 2 Output.
Real time readback of comparator 2.
bits : 17 - 17 (1 bit)
access : read-write
LPWREN : Comparator Low power mode enable
If '1' comparator will remain enabled in STOP/SPD power modes.
bits : 24 - 24 (1 bit)
access : read-write
CSCAN Cycle Count Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLE_CNT : CSCAN Cycle Count
bits : 0 - 3 (4 bit)
access : read-write
MASK : Scan Mask Register
If MASK[n] is set then GPIOB[n] is included in scan of capacitive sensing.
bits : 16 - 31 (16 bit)
access : read-write
CSCAN Count Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : CSCAN Count
Count result of single scan.
bits : 0 - 15 (16 bit)
access : read-write
CSCAN Interrupt Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT : CSCAN Interrupt active
Write '1' to clear.
bits : 0 - 0 (1 bit)
access : read-write
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