\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
System Power Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LXTEN : External 32.768 KHz Crystal Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable (default)
#1 : 1
enable
End of enumeration elements list.
HIRCEN : HIRC Oscillator Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable (default)
End of enumeration elements list.
LIRCEN : LIRC Oscillator Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable
#1 : 1
enable (default)
End of enumeration elements list.
HXTEN : HXT Oscillator Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable (default)
#1 : 1
enable
End of enumeration elements list.
STOPEN : Stop
Set to '1' and issue WFI/WFE instruction to enter STOP mode.
bits : 9 - 9 (1 bit)
access : read-write
SPDEN : Standby Power Down (SPD) Bit
Set to '1' and issue WFI/WFE instruction to enter SPD mode.
bits : 10 - 10 (1 bit)
access : read-write
DPDEN : Deep Power Down (DPD) Bit
Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 11 - 11 (1 bit)
access : read-write
HOLDIO : When entering SPD mode, IO state is automatically held If this bit is set to '1' then this sate upon resuming full power mode will be hold until the RELEASE_IO bit is written '1'
bits : 12 - 12 (1 bit)
access : read-write
RELEASEIO : Write '1' to this bit to release IO state after exiting SPD if hold request was made with the HOLD_IO bit.
bits : 13 - 13 (1 bit)
access : read-write
IOSTATE : '1': IO held from SPD '0': IO released.
bits : 14 - 14 (1 bit)
access : read-write
WKPINEN : Wakeup Pin Enabled Control
Determines whether WAKEUP pin is enabled in DPD mode.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
enabled
#1 : 1
disabled
End of enumeration elements list.
LIRCDPDEN : OSC10k Enabled Control
Determines whether OSC10k is enabled in DPD mode. If OSC10k is disabled, device cannot wake from DPD with SELWKTMR delay.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
enabled
#1 : 1
disabled
End of enumeration elements list.
FLASHEN : Flash ROM Control Enable/Disable
Bit [19]: for Stop mode operation
Bit [18]: for Sleep mode operation
1: Turn off flash
0: Normal
Note: It takes 10us to turn on the flash to normal
bits : 18 - 19 (2 bit)
access : read-write
WKPINWKF : Pin Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a high to low transition of the WAKEUP pin. Flag is cleared when DPD mode is entered.
bits : 24 - 24 (1 bit)
access : read-write
TMRWKF : Timer Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10khz oscillator. Flag is cleared when DPD mode is entered.
bits : 25 - 25 (1 bit)
access : read-write
PORWKF : POR Wakeup Flag
Read Only. This flag indicates that wakeup of device was requested with a power-on reset. Flag is cleared when DPD mode is entered.
bits : 26 - 26 (1 bit)
access : read-write
WKPUEN : Wakeup Pin Pull-up Control
This signal is latched in deep power down and preserved.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
pull-up enable
#1 : 1
tri-state (default)
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Select
Ensure that related clock sources (pre-select and new-select) are enabled before updating register.
These bits are protected, to write to bits first perform the unlock sequence.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from HIRC. (deafult)
#001 : 1
clock source from LXT
#010 : 2
clock source from LIRC
#011 : 3
clock source from HXT
End of enumeration elements list.
STCLKSEL : MCU Cortex_M0 SYST Clock Source Select
These bits are protected, to write to bits first perform the unlock sequence.
Note that to use STCLKSEL as source of SysTic timer the CLKSRC bit of SYST_CSR must be set to 0.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from LIRC
#001 : 1
clock source from LXT.
clock source from HCLK÷2 (Default)
#010 : 2
clock source from LIRC divided by 2
#011 : 3
clock source from HIRC divided by 2
End of enumeration elements list.
HIRCFSEL : High Frequency RC Oscilltor Frequency Select Register.
These bits are protected, to write to bits first perform the unlock sequence.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim for 49.152MHz selected
#01 : 1
Trim for 32.768MHz selected
#10 : 2
Trim for reserved
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : WDT Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from HIRC
#01 : 1
clock source from LXT
#10 : 2
clock source from HCLK/2048 clock
#11 : 3
clock source from LIRC.(default)
End of enumeration elements list.
SDADCSEL : SD ADC Clock Source Select (output is MCLK after clock enable)
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from HCLK/(SDADCDIV+1). (default)
#01 : 1
clock source from HXT
Reserved
End of enumeration elements list.
DPWMSEL : Differential Speaker Driver PWM Clock Source Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from HCLK/(DPWMDIV+1). (default)
#01 : 1
clock source from HXT
Reserved
End of enumeration elements list.
TMR0SEL : TIMER0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from LIRC
#001 : 1
clock source from LXT.
clock source from internal HCLK.(default)
#010 : 2
clock source from HXT
#011 : 3
clock source from external pin (GPIOA[10])
End of enumeration elements list.
TMR1SEL : TIMER1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from LIRC
#001 : 1
clock source from LXT.
clock source from HCLK.(default)
#010 : 2
clock source from HXT
#011 : 3
clock source from external pin (GPIOA[11])
End of enumeration elements list.
SARADCSEL : SAR ADC Clock Source Select
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from HCLK (default)
#01 : 1
clock source from LIRC
#10 : 2
clock source from HIRC
#11 : 3
clock source from LXT
End of enumeration elements list.
PWM0CH01SEL : PWM0CH01 Clock Source Select
PWM0 CH0 and CH1 uses the same clock source, and pre-scaler
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from LIRC
#01 : 1
clock source from LXT
#10 : 2
clock source from HCLK
#11 : 3
clock source from HIRC.(default)
End of enumeration elements list.
PWM0CH23SEL : PWM0CH23 Clock Source Select
PWM0 CH2 and CH3 uses the same clock source, and pre-scaler
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from LIRC
#01 : 1
clock source from LXT
#10 : 2
clock source from HCLK
#11 : 3
clock source from HIRC.(default)
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
BIQDIV : BIQ Clock Divide Number From HCLK Clock Source
bits : 4 - 7 (4 bit)
access : read-write
UARTDIV : UART Clock Divide Number From UART Clock Source
bits : 8 - 11 (4 bit)
access : read-write
DPWMDIV : DPWM Clock Divide Number From HCLK Clock Source
bits : 12 - 15 (4 bit)
access : read-write
SDADCDIV : SDADC Clock Divide Number From ADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write
SARADCDIV : SARADC Clock Divide Number From ADC Clock Source
bits : 24 - 31 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S0SEL : I2S0 Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from internal 10kHz oscillator.(default)
#01 : 1
clock source from external 32kHz crystal clock
#10 : 2
clock source from HCLK
#11 : 3
clock source from HIRC
End of enumeration elements list.
UART1DIV : UART1 Clock Divide Number From UART Clock Source
bits : 8 - 11 (4 bit)
access : read-write
Sleep Clock Source Select Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKCKEN : CPU Clock Sleep Enable (HCLK)
Must be left as '1' for normal operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PDMACKEN : PDMA Controller Sleep Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Sleep Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
WDTCKEN : Watchdog Sleep Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RTCCKEN : Real-time- Sleep Clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR0CKEN : Timer0 Sleep Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR1CKEN : Timer1 Sleep Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
I2C0CKEN : I2C0 Sleep Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SPI1CHEN : SPI1 Sleep Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SPI0CKEN : SPI0 Sleep Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DPWMCKEN : Differential PWM Speaker Driver Sleep Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
UART1CKEN : UART1 Sleep Clock Enable Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
UART0CKEN : UART0 Sleep Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SARADCCKEN : SARADC Sleep Clock Enable Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
BIQALCKEN : BIQ and ALCSleep Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PWM0CH01CKEN : PWM0CH0 and PWM0CH1 Block Sleep Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PWM0CH23CKEN : PWM0CH2 and PWM0CH3 Block Sleep Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SDADCCKEN : Delta-Sigma Analog-digital-converter (ADC) Sleep Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
I2SCKEN : I2S Sleep Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ANACKEN : Analog Block Sleep Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Power State Flag Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSF : Deep Sleep Flag
This flag is set if core logic was placed in Deep Sleep mode. Write '1' to clear flag.
bits : 0 - 0 (1 bit)
access : read-write
STOPF : Stop Flag
This flag is set if core logic was stopped but not powered down. Write '1' to clear flag.
bits : 1 - 1 (1 bit)
access : read-write
SPDF : Powered Down Flag
This flag is set if core logic was powered down to Standby (SPD). Write '1' to clear flag.
bits : 2 - 2 (1 bit)
access : read-write
Debug Port Power Down Disable Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISPDREQ : Disable Power Down
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable power down requests
#1 : 1
Disable power down requests
End of enumeration elements list.
ICECLKST : ICECLKST Pin State
Read Only. Current state of ICE_CLK pin.
bits : 6 - 6 (1 bit)
access : read-write
ICEDATST : ICEDATST Pin State
Read Only. Current state of ICE_DAT pin.
bits : 7 - 7 (1 bit)
access : read-write
Deep Power Down 10K Wakeup Timer
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELWKTMR : Select Wakeup Timer
WAKEUP after 64* (SELWKTMR+1) OSC10k clocks (6.4 * (SELWKTMR+1) ms)
bits : 0 - 13 (14 bit)
access : read-write
WKTMRSTS : Current Wakeup Timer Setting
Read-Only. Read back of the current WAKEUP timer setting. This value is updated with SELWKTMR upon entering DPD mode.
bits : 16 - 29 (14 bit)
access : read-write
WAKE10KEN : Enable WAKE from DPD on 10kHz timer
bits : 31 - 31 (1 bit)
access : read-write
AHB Device Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKEN : CPU Clock Enable (HCLK)
Must be left as 1 for normal operation.
bits : 0 - 0 (1 bit)
access : read-write
PDMACKEN : PDMA Controller Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
To disable the PDMA engine clock
#1 : 1
To enable the PDMA engine clock
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
To disable the Flash ISP engine clock
#1 : 1
To enable the Flash ISP engine clock
End of enumeration elements list.
APB Device Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTCKEN : Watchdog Clock Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RTCCKEN : Real-time-clock APB Interface Clock Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR0CKEN : Timer0 Clock Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR1CKEN : Timer1 Clock Enable Control
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
I2C0CKEN : I2C0 Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SPI1CKEN : SPI1 Clock Enable Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SPI0CKEN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
DPWMCKEN : Differential PWM Speaker Driver Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
UART1CKEN : UART1 Clock Enable Control
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
UART0CKEN : UART0 Clock Enable Control
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SARADCKEN : SAR Analog-digital-converter (ADC) Clock Enable Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
BIQALCKEN : BIQ and ALC Clock Enable Control
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PWM0CH01CKEN : PWM0CH0 and PWM0CH1 Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PWM0CH23CKEN : PWM0CH2 and PWM0CH3 Block Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SDADCCKEN : Delta-Sigma Analog-digital-converter (ADC) Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
I2S0CKEN : I2S Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ANACKEN : Analog Block Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
Deep Power Down State Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPDSTSWR : DPD State Write Register
Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
bits : 0 - 7 (8 bit)
access : read-write
DPDSTSRD : DPD State Read Back
Read back of CLK_DPDSTATE register. This register was preserved from last DPD event .
bits : 8 - 15 (8 bit)
access : read-write
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