\n
address_offset : 0x0 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTCNT : Clear Watchdog Timer
Set this bit will clear the Watchdog timer.
NOTE: This bit will auto clear after few clock cycle
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Reset the contents of the Watchdog timer
End of enumeration elements list.
RSTEN : Watchdog Timer Reset Enable
Setting this bit will enable the Watchdog timer reset function.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Watchdog timer reset function
#1 : 1
Enable Watchdog timer reset function
End of enumeration elements list.
RSTF : Watchdog Timer Reset Flag
When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If RSTEN is disabled, then the Watchdog timer has no effect on this bit.
NOTE: This bit is cleared by writing 1 to this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer reset has not occurred
#1 : 1
Watchdog timer reset has occurred
End of enumeration elements list.
IF : Watchdog Timer Interrupt Flag
If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a timeout period has elapsed.
NOTE: This bit is cleared by writing 1 to this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Watchdog timer interrupt has not occurred
#1 : 1
Watchdog timer interrupt has occurred
End of enumeration elements list.
INTEN : Watchdog Timer Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Watchdog timer interrupt
#1 : 1
Enable the Watchdog timer interrupt
End of enumeration elements list.
WDTEN : Watchdog Timer Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the Watchdog timer (This action will reset the internal counter)
#1 : 1
Enable the Watchdog timer
End of enumeration elements list.
TOUTSEL : Watchdog Timer Interval Select
These three bits select the timeout interval for the Watchdog timer, a watchdog reset will occur 1024 clock cycles later if WDG not reset. The timeout is given by:
Where WDT_CLK is the period of the Watchdog Timer clock source.
bits : 8 - 10 (3 bit)
access : read-write
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