\n
address_offset : 0x0 Bytes (0x0)
size : 0x78 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COEFFDAT : Coefficient Data
bits : 0 - 31 (32 bit)
access : read-write
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 2nd Stage BIQ Coefficients
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 3rd Stage BIQ Coefficients
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 4st Stage BIQ Coefficients
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 5nd Stage BIQ Coefficients
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B0 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B1 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient A2 in H(z) Transfer Function
(3.16 Format) - 6rd Stage BIQ Coefficients
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Coefficient B2 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQ Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BIQEN : BIQ Filter Start to Run
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BIQ filter is not processing
#1 : 1
BIQ filter is on
End of enumeration elements list.
HPFON : High Pass Filter On
Note :
If this register is on, BIQ only 5 stage left.for user.
SDADC path sixth stage coefficient is for HPF filter coefficient.
DPWM path first stage coefficient is for HPF filter coefficient.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
disable high pass filter
#1 : 1
enable high pass filter
End of enumeration elements list.
PATHSEL : AC Path Selection for BIQ
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
used in SDADC path
#1 : 1
used in DPWM path
End of enumeration elements list.
DLCOEFF : Move BIQ Out of Reset State
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
BIQ filter is in reset state
#1 : 1
When this bit is on, the default coefficients will be downloaded to the coefficient ram automatically in 32 internal system clocks. Processor must delay enough time before changing the coefficients or turn the BIQ on
End of enumeration elements list.
SDADCWNSR : SDADC Down Sample
001--- 1x (no down sample)
010 --- 2x
011 --- 3x
100 --- 4x
11 0--- 6x
Others reserved
bits : 4 - 6 (3 bit)
access : read-write
PRGCOEFF : Programming Mode Coefficient Control Bit
This bit must be turned off when BIQEN is on.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Coefficient RAM is in normal mode
#1 : 1
coefficient RAM is under programming mode
End of enumeration elements list.
DPWMPUSR : DPWM Path Up Sample Rate (From SRDIV Result)
0001 --- up 1x ( no up sample)
0010 --- up 2x
0011 --- up 3x
0100 --- up 4x
0110 --- up 6x
Others reserved
bits : 8 - 10 (3 bit)
access : read-write
STAGE : BIQ Stage Number Control
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
6 stage
#1 : 1
5 stage
End of enumeration elements list.
SRDIV : SR Divider
bits : 16 - 28 (13 bit)
access : read-write
BIQ Status Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BISTEN : RAM BIST testing Enable for internal use
bits : 0 - 0 (1 bit)
access : read-write
BISTFAILED : RAM BIST testing FAILED indicator for internal use
bits : 1 - 1 (1 bit)
access : read-write
BISTDONE : RAM BIST testing DONE flag for internal use
bits : 2 - 2 (1 bit)
access : read-write
RAMINITF : Coefficient Ram Initial Default Done Flag
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
initial default value done
#1 : 1
still working on
End of enumeration elements list.
Coefficient A1 in H(z) Transfer Function
(3.16 Format) - 1st Stage BIQ Coefficients
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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