\n
address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x50 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x5C Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
SAR ADC Data Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : A/D Conversion Result
This field contains conversion result of SARADC.
12-bit SARADC conversion result with unsigned format.
bits : 0 - 11 (12 bit)
access : read-only
OV : Overrun Flag (Read Only)
Note: If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone. It is cleared by hardware after DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] is recent conversion result
#1 : 1
Data in RESULT[11:0] is overwritten
End of enumeration elements list.
VALID : Valid Flag (Read Only)
Note: This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] bits is not valid
#1 : 1
Data in RESULT[11:0] bits is valid
End of enumeration elements list.
SAR ADC Data Register 4
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 5
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 6
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 7
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 8
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 9
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 10
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 11
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEF : A/D Conversion End Flag
A status flag that indicates the end of A/D conversion.
ADEF is set to 1 at these two conditions:
1. When A/D conversion ends in Single mode.
2. When A/D conversion ends on all specified channels in Scan mode.
Note: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write
ADCMPF0 : Compare Flag
When the selected channel A/D conversion result meets setting condition in SARADC_CMP0 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in DAT register does not meet CMP0 register
#1 : 1
Conversion result in DAT register meets CMP0 register
End of enumeration elements list.
ADCMPF1 : Compare Flag
When the selected channel A/D conversion result meets setting condition in SARADC_CMP1 then this bit is set to 1. And it is cleared by writing 1 to self.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in DAT register does not meet CMP1 register
#1 : 1
Conversion result in DAT register meets CMP1 register
End of enumeration elements list.
BUSY : BUSY/IDLE (Read Only)
This bit is mirror of as SWTRG bit in CTL.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel (Read Only)
bits : 4 - 7 (4 bit)
access : read-only
VALID : Data Valid Flag (Read Only)
It is a mirror of VALID bit in DATx.
bits : 8 - 23 (16 bit)
access : read-only
SAR ADC PDMA Current Transfer Data
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : SAR ADC PDMA Current Transfer Data Register (Read Only)
When PDMA transferring, read this register can monitor current PDMA transfer data.
Current PDMA transfer data is the content of DAT0 ~ DAT11.
bits : 0 - 17 (18 bit)
access : read-only
SAR ADC Analog Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR_SE_MODE : SE mode selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#1 : 1
SARADC in single ended mode
End of enumeration elements list.
ReservedSAR_VCMsel : ReservedSAR VCM voltage
0---- select internal VCM
1 --- select external VCM
bits : 16 - 16 (1 bit)
access : read-write
ReservedSAR_cur : ReservedSAR current
0 --- low bias current for comparator
1 --- high bias current for comparator
bits : 17 - 17 (1 bit)
access : read-write
SAR_VREF : VREF selection
0 -- select VCCA as VREF
1 -- select MICBIAS as VREF
bits : 18 - 18 (1 bit)
access : read-write
SAR ADC Control Register
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : A/D Converter Enable Bit
Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADCIE : A/D Interrupt Enable Bit
A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
OPMODE : A/D Converter Operation Mode
When changing the operation mode, software should disable SWTRG bit firstly.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Single conversion
#01 : 1
Reserved
#10 : 2
Single-cycle scan
#11 : 3
Continuous scan
End of enumeration elements list.
HWTRGSEL : Hardware Trigger Source Selection
Software should disable TRGEN and SWTRG before change HWTRGSEL.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
End of enumeration elements list.
HWTRGCOND : External Trigger Condition
These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Falling edge
#11 : 3
Rising edge
End of enumeration elements list.
HWTRGEN : Hardware Trigger Enable Bit
Enable or disable triggering of A/D conversion by hardware (external STADC pin or PWM Center-aligned trigger).
SARADC hardware trigger function is only supported in single-cycle scan mode.
If hardware trigger mode, the SWTRG bit can be set to 1 by the selected hardware trigger source.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
PDMAEN : PDMA Transfer Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer in DAT 0~11 Enabled
End of enumeration elements list.
SWTRG : A/D Conversion Start
SWTRG bit can be set to 1 from three sources: software, external pin STADC. SWTRG will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode. In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stops and A/D converter enter idle state
#1 : 1
Conversion starts
End of enumeration elements list.
SAR ADC Channel Enable Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Analog Input Channel Enable Bit
Set CHEN[11:0] to enable the corresponding analog input channel 11 ~ 0.
Note: Keep 0 for [15:12]
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
SARADC input channel Disabled
1 : 1
SARADC input channel Enabled
End of enumeration elements list.
ReservedSAR_Vref_sel : ReservedAnalog reference voltage
0 --- use input [15] Note: no MUX selection to input[15] for user
1 ---- measure voltage on vref_bandgap instead of voltage on input [15]
bits : 16 - 16 (1 bit)
access : read-write
ReservedDIFFCHEN : ReservedDifferencial channel mask enable
bits : 20 - 23 (4 bit)
access : read-write
SAR ADC Compare Register 0
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : Compare Enable Bit
Note: Set this bit to 1 to enable SARADC controller to compare CMPDAT[11:0] with specified channel conversion result when converted data is loaded into DAT register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
ADCMPIE : Compare Interrupt Enable Bit
Note: If the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMCNT, ADCMPF bit will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition
Note: When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (CMPx[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (CMPx[27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Channel 0 conversion result is selected to be compared
#0001 : 1
Channel 1 conversion result is selected to be compared
#0010 : 2
Channel 2 conversion result is selected to be compared
#0011 : 3
Channel 3 conversion result is selected to be compared
#0100 : 4
Channel 4 conversion result is selected to be compared
#0101 : 5
Channel 5 conversion result is selected to be compared
#0110 : 6
Channel 6 conversion result is selected to be compared
#0111 : 7
Channel 7 conversion result is selected to be compared
#1000 : 8
Channel 8 conversion result is selected to be compared
#1001 : 9
Channel 9 conversion result is selected to be compared
#1010 : 10
Channel 10 conversion result is selected to be compared
#1011 : 11
Channel 11 conversion result is selected to be compared
#1100 : 12
Reserved
#1101 : 13
Reserved
#1110 : 14
Reserved
#1111 : 15
Reserved
End of enumeration elements list.
CMPMCNT : Compare Match Count
When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPDAT : Comparison Data
The 12-bit data is used to compare with conversion result of specified channel.
When ADCFMbit is set to 0, SARADC comparator compares CMPDAT with conversion result with unsigned format. CMPDAT should be filled in unsigned format.
When ADCFMbit is set to 1, SARADC comparator compares CMPDAT with conversion result with 2'complement format. CMPDAT should be filled in 2'complement format.
bits : 16 - 27 (12 bit)
access : read-write
SAR ADC Compare Register 1
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 2
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SAR ADC Data Register 3
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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