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SYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x30 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x54 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x110 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_IRCTCTL (IRCTCTL)

SYS_PASMTEN (PASMTEN)

SYS_PBSMTEN (PBSMTEN)

SYS_GPA_MFP (GPA_MFP)

SYS_GPB_MFP (GPB_MFP)

SYS_RSTSTS (RSTSTS)

SYS_WKCTL (WKCTL)

SYS_IPRST0 (IPRST0)

SYS_IPRST1 (IPRST1)


SYS_PDID (PDID)

Product ID
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SYS_PDID SYS_PDID read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDID

PDID : Product Identifier Chip identifier for ISD9300 series.
bits : 0 - 31 (32 bit)
access : read-only


SYS_REGLCTL (REGLCTL)

Register Lock Control
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_REGLCTL SYS_REGLCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGLCTL

REGLCTL : Protected Register Unlock Register
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Protected registers are locked. Any write to the target register is ignored

#1 : 1

Protected registers are unlocked

End of enumeration elements list.


SYS_IRCTCTL (IRCTCTL)

Oscillator Frequency Adjustment control register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRCTCTL SYS_IRCTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ0SEL RGE0SEL FREQ1SEL RGE1SEL

FREQ0SEL : Frequency Select 8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
bits : 0 - 7 (8 bit)
access : read-write

RGE0SEL : Range Bit For Oscillator
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

high range

#1 : 1

low range

End of enumeration elements list.

FREQ1SEL : Frequency Select 8 bit trim for oscillator. ANA_TRIM[7:5] are 8 coarse trim ranges which overlap in frequency. ANA_TRIM[4:0] are 32 fine trim steps of approximately 0.5% resolution.
bits : 16 - 23 (8 bit)
access : read-write

RGE1SEL : Range Bit For Oscillator
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

high range

#1 : 1

low range

End of enumeration elements list.


SYS_PASMTEN (PASMTEN)

GPIOA input type control register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PASMTEN SYS_PASMTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMTEN16 SMTEN17 SMTEN18 SMTEN19 SMTEN20 SMTEN21 SMTEN22 SMTEN23 SMTEN24 SMTEN25 SMTEN26 SMTEN27 SMTEN28 SMTEN29 SMTEN30 SMTEN31

SMTEN16 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN17 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN18 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN19 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN20 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN21 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN22 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN23 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN24 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN25 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN26 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN27 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN28 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN29 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN30 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN31 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOA[15:0] I/O input Schmitt Trigger disabled

#1 : 1

GPIOA[15:0] I/O input Schmitt Trigger enabled

End of enumeration elements list.


SYS_PBSMTEN (PBSMTEN)

GPIOB input type control register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_PBSMTEN SYS_PBSMTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMTEN16 SMTEN17 SMTEN18 SMTEN19 SMTEN20 SMTEN21 SMTEN22 SMTEN23

SMTEN16 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN17 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN18 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN19 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN20 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN21 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN22 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.

SMTEN23 : Schmitt Trigger This register controls whether the GPIO input buffer Schmitt trigger is enabled.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger disabled

#1 : 1

GPIOB(port 0 ~ port 7) I/O input Schmitt Trigger enabled

End of enumeration elements list.


SYS_GPA_MFP (GPA_MFP)

GPIOA multiple alternate functions control register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPA_MFP SYS_GPA_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA0MFP PA1MFP PA2MFP PA3MFP PA4MFP PA5MFP PA6MFP PA7MFP PA8MFP PA9MFP PA10MFP PA11MFP PA12MFP PA13MFP PA14MFP PA15MFP

PA0MFP : Alternate Function Setting For PA0MFP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_MOSI0

#10 : 2

MCLK

End of enumeration elements list.

PA1MFP : Alternate Function Setting For PA1MFP
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_SCLK

#10 : 2

I2C_SCL

End of enumeration elements list.

PA2MFP : Alternate Function Setting For PA2MFP
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_SSB0

End of enumeration elements list.

PA3MFP : Alternate Function Setting For PA3MFP
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_MISO0

#10 : 2

I2C_SDA

End of enumeration elements list.

PA4MFP : Alternate Function Setting For PA4MFP
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_FS

End of enumeration elements list.

PA5MFP : Alternate Function Setting For PA5MFP
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_BCLK

#11 : 3

SPI_SSB1

End of enumeration elements list.

PA6MFP : Alternate Function Setting For PA6MFP
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_SDI

#10 : 2

UART_TX

End of enumeration elements list.

PA7MFP : Alternate Function Setting For PA7MFP
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_SDO

End of enumeration elements list.

PA8MFP : Alternate Function Setting For PA8MFP
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

UART_TX

#10 : 2

CMP12

#11 : 3

PWM0CH2

End of enumeration elements list.

PA9MFP : Alternate Function Setting For PA9MFP
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

UART_RX

#10 : 2

CMP13

#11 : 3

PWM0CH3

End of enumeration elements list.

PA10MFP : Alternate Function Setting For PA10MFP
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2C_SDA

#10 : 2

CMP14

#11 : 3

UART_RTSn

End of enumeration elements list.

PA11MFP : Alternate Function Setting For PA11MFP
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2C_SCL

#10 : 2

CMP15

#11 : 3

UART_CTSn

End of enumeration elements list.

PA12MFP : Alternate Function Setting For PA12MFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH0

#10 : 2

SPKP

#11 : 3

I2S_FS

End of enumeration elements list.

PA13MFP : Alternate Function Setting For PA13MFP
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH1

#10 : 2

SPKM

#11 : 3

I2S_BCLK

End of enumeration elements list.

PA14MFP : Alternate Function Setting For PA14MFP
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

TM0

#10 : 2

SDCLK

#11 : 3

PWM1CH0

End of enumeration elements list.

PA15MFP : Alternate Function Setting For PA15MFP
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

TM1

#10 : 2

SDIN

#11 : 3

PWM1CH1

End of enumeration elements list.


SYS_GPB_MFP (GPB_MFP)

GPIOB multiple alternate functions control register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_GPB_MFP SYS_GPB_MFP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0MFP PB1MFP PB2MFP PB3MFP PB4MFP PB5MFP PB6MFP PB7MFP PB8MFP PB9MFP PB10MFP PB11MFP PB12MFP PB13MFP PB14MFP PB15MFP

PB0MFP : Alternate Function Setting For PB0MFP
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_SSB1

#10 : 2

CMP0

#11 : 3

SPI_SSB0

End of enumeration elements list.

PB1MFP : Alternate Function Setting For PB1MFP
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

MCLK

#10 : 2

CMP1

#11 : 3

SPI_SSB1

End of enumeration elements list.

PB2MFP : Alternate Function Setting For PB2MFP
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2C_SCL

#10 : 2

CMP2

#11 : 3

SPI_SCLK

End of enumeration elements list.

PB3MFP : Alternate Function Setting For PB3MFP
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2C_SDA

#10 : 2

CMP3

#11 : 3

SPI_MISO0

End of enumeration elements list.

PB4MFP : Alternate Function Setting For PB4MFP
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH0B

#10 : 2

CMP4

#11 : 3

SPI_MOSI0

End of enumeration elements list.

PB5MFP : Alternate Function Setting For PB5MFP
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH1B

#10 : 2

CMP5

#11 : 3

SPI_MISO1

End of enumeration elements list.

PB6MFP : Alternate Function Setting For PB6MFP
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_SDI

#10 : 2

CMP6

#11 : 3

SPI_MOSI1

End of enumeration elements list.

PB7MFP : Alternate Function Setting For PB7MFP
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_SDO

#10 : 2

CMP7

End of enumeration elements list.

PB8MFP : Alternate Function Setting For PB8MFP
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_FS(master)

#10 : 2

CMP8

End of enumeration elements list.

PB9MFP : Alternate Function Setting For PB9MFP
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_BCLK(master)

#10 : 2

CMP9

End of enumeration elements list.

PB10MFP : Alternate Function Setting For PB10MFP
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#10 : 2

CMP10

End of enumeration elements list.

PB11MFP : Alternate Function Setting For PB11MFP
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

I2S_SDO

#10 : 2

CMP11

End of enumeration elements list.

PB12MFP : Alternate Function Setting For PB12MFP
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_MISO1

#10 : 2

PWM1CH0

#11 : 3

PWM1CH1B

End of enumeration elements list.

PB13MFP : Alternate Function Setting For PB13MFP
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

SPI_MOSI1

#10 : 2

PWM1CH1

#11 : 3

PWM1CH0B

End of enumeration elements list.

PB14MFP : Alternate Function Setting For PB14MFP
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH2

#10 : 2

UART_TX

#11 : 3

PWM0CH3B

End of enumeration elements list.

PB15MFP : Alternate Function Setting For PB15MFP
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

#00 : 0

GPIO

#01 : 1

PWM0CH3

#11 : 3

PWM0CH2B

End of enumeration elements list.


SYS_RSTSTS (RSTSTS)

System Reset Source Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_RSTSTS SYS_RSTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CORERSTF WDTRF SYSRF PMURSTF CPURF WKRSTF DPDRSTF PORF

CORERSTF : Reset Source From CORE The CORERSTF flag is set if the core has been reset. Possible sources of reset are a Power-On Reset (POR), RESETn Pin Reset or PMU reset. This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CORE

#1 : 1

Core was reset by hardware block

End of enumeration elements list.

WDTRF : Reset Source From WDG The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. This bit is cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from Watch-Dog

#1 : 1

The Watch-Dog module issued the reset signal to reset the system

End of enumeration elements list.

SYSRF : Reset Source From MCU The SYSRF flag is set if the previous reset source originates from the Cortex_M0 kernel. This bit is cleared by writing 1 to itself.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from MCU

#1 : 1

The Cortex_M0 MCU issued a reset signal to reset the system by software writing 1 to bit SYSRESTREQ(SYSCTL_AIRCTL[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel

End of enumeration elements list.

PMURSTF : Reset Source From PMU The PMURSTF flag is set if the PMU. This bit is cleared by writing 1 to itself.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from PMU

#1 : 1

PMU reset the system from a power down/standby event

End of enumeration elements list.

CPURF : Reset Source From CPU The CPURF flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) with a 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit is cleared by writing 1 to itself.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

No reset from CPU

#1 : 1

The Cortex-M0 CPU kernel and FMC has been reset by software setting CPURST to 1

End of enumeration elements list.

WKRSTF : Wakeup Pin Reset Flag The WKRSTF flag is set by hardware if device has powered up from deep power down (DPD) due to action of the WAKEUP pin. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

No detected

#1 : 1

A power on was triggered by WAKEUP pin

End of enumeration elements list.

DPDRSTF : Deep Power Down Reset Flag The DPDRSTF flag is set by hardware if device has powered up due to the DPD timer function. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

No detected

#1 : 1

A power on was triggered by DPD timer

End of enumeration elements list.

PORF : Power On Reset Flag The PORF flag is set by hardware if device has powered up from a power on reset condition or standby power down. This bit is cleared by writing 1 to itself. Writing 1 to this bit will clear bits PORF, DPDRSTF, and WKRSTF
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

No detected

#1 : 1

A power on Reset has occurred

End of enumeration elements list.


SYS_WKCTL (WKCTL)

WAKEUP pin control register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_WKCTL SYS_WKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WKDIN WKPUEN WKOENB WKDOUT

WKDIN : State Of Wakeup Pin Read only.
bits : 0 - 0 (1 bit)
access : read-write

WKPUEN : Wakeup Pin Pull-Up Control This signal is latched in deep power down and preserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

pull-up enable

#1 : 1

tri-state (default)

End of enumeration elements list.

WKOENB : Wakeup Pin Output Enable Bar
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

drive WKDOUT to pin

#1 : 1

tri-state (default)

End of enumeration elements list.

WKDOUT : Wakeup Output State Default set 0
bits : 3 - 3 (1 bit)
access : read-write


SYS_IPRST0 (IPRST0)

IP Reset Control Resister0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IPRST0 SYS_IPRST0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIPRST CPURST PDMARST

CHIPRST : CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after the 2 clock cycles. CHIPRST has same behavior as POR reset, all the chip modules are reset and the chip configuration settings from flash are reloaded. This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal

#1 : 1

Reset CHIP

End of enumeration elements list.

CPURST : CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles This bit is a protected bit, to program first issue the unlock sequence (see Protected Register Lock Key Register (SYS_REGLCTL))
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal

#1 : 1

Reset CPU

End of enumeration elements list.

PDMARST : PDMA Controller Reset Set 1 will generate a reset signal to the PDMA Block. User needs to set this bit to 0 to release from the reset state
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal operation

#1 : 1

PDMA IP reset

End of enumeration elements list.


SYS_IPRST1 (IPRST1)

IP Reset Control Resister1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IPRST1 SYS_IPRST1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TMR0RST TMR1RST I2C0RST SPI0RST DPWMRST UART0RST BIQRST CRCRST PWM0RST PWM1RST ACMPRST EADCRST I2S0RST ANARST

TMR0RST : Timer0 Controller Reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

DPWMRST : DPWM Speaker Driver Reset
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

BIQRST : Biquad Filter Block Reset
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

CRCRST : CRC Generation Block Reset
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

PWM1RST : PWM1 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

ACMPRST : Analog Comparator Reset
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

EADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

I2S0RST : I2S Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.

ANARST : Analog Block Control Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Normal Operation

#1 : 1

Reset

End of enumeration elements list.



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