\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x34 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x134 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x234 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x300 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x334 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE00 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE0C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0xE80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF00 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xF0C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
PDMA Control Register of Channel 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : PDMA Channel Enable
Setting this bit to 1 enables PDMA's operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
Note: SWRST will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
SWRST : Software Engine Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of the control register will not be cleared. This bit will auto clear after a few clock cycles
End of enumeration elements list.
MODESEL : PDMA Mode Select
This parameter selects to transfer direction of the PDMA channel. Possible values are:
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Memory to Memory mode (SRAM-to-SRAM)
#01 : 1
IP to Memory mode (APB-to-SRAM)
#10 : 2
Memory to IP mode (SRAM-to-APB)
End of enumeration elements list.
SASEL : Source Address Select
This parameter determines the behavior of the current source address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Source address is incremented
#01 : 1
RESERVED
#10 : 2
Transfer Source address is fixed
#11 : 3
Transfer Source address is wrapped. When PDMA_CURBCCH (Current Byte Count) equals zero, the PDMA_CURSACH (Current Source Address) and PDMA_CURBCCH registers will be reloaded from the SAR (Source Address) and PDMA_TXBCCH (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN aaa 0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
End of enumeration elements list.
DASEL : Destination Address Select
This parameter determines the behavior of the current destination address register with each PDMA transfer. It can either be fixed, incremented or wrapped.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Destination Address is incremented
#01 : 1
RESERVED
#10 : 2
Transfer Destination Address is fixed (Used when data transferred from multiple addresses to a single destination such as peripheral FIFO input)
#11 : 3
Transfer Destination Address is wrapped. When PDMA_CURBCCH (Current Byte Count) equals zero, the PDMA_CURDACH (Current Destination Address) and PDMA_CURBCCH registers will be reloaded from the PDMA_DSCTn_ENDDA (Destination Address) and PDMA_TXBCCHn (Byte Count) registers automatically and PDMA will start another transfer. Cycle continues until software sets PDMA_EN=0. When PDMA_EN is disabled, the PDMA will complete the active transfer but the remaining data in the SBUF will not be transferred to the destination address
End of enumeration elements list.
WAINTSEL : Wrap Interrupt Select
x1xx: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when half each PDMA transfer is complete. For example if BYTECNT aaa 32 then an interrupt could be generated when 16 bytes were sent.
xxx1: If this bit is set, and wraparound mode is in operation a Wrap Interrupt can be generated when each PDMA transfer is wrapped. For example if BYTECNT aaa 32 then an interrupt could be generated when 32 bytes were sent and PDMA wraps around.
x1x1: Both half and w interrupts generated.
bits : 12 - 15 (4 bit)
access : read-write
TXWIDTH : Peripheral Transfer Width Select
This parameter determines the data width to be transferred each PDMA transfer operation.
Note: This field is meaningful only when MODESEL is IP to Memory mode (APB-to-Memory) or Memory to IP mode (Memory-to-APB).
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
One word (32 bits) is transferred for every PDMA operation
#01 : 1
One byte (8 bits) is transferred for every PDMA operation
#10 : 2
One half-word (16 bits) is transferred for every PDMA operation
#11 : 3
RESERVED
End of enumeration elements list.
TXEN : Trigger Enable - Start A PDMA Operation
Note: When PDMA transfer completed, this bit will be cleared automatically.
If a bus error occurs, all PDMA transfer will be stopped. Software must reset PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Write: no effect. Read: Idle/Finished
#1 : 1
Enable PDMA data read or write transfer
End of enumeration elements list.
PDMA Internal Buffer Pointer Register of Channel 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BURPTR : PDMA Internal Buffer Pointer Register (Read Only)
A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
bits : 0 - 3 (4 bit)
access : read-only
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x104 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x108 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x10C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x11C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x120 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x124 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x134 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x138 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Current Source Address Register of Channel 0
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURSA : PDMA Current Source Address Register (Read Only)
This register returns the source address from which the PDMA transfer is occurring. This register is loaded from ENDSA when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Current Destination Address Register of Channel 0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURDA : PDMA Current Destination Address Register (Read Only)
This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from PDMA_DSCTn_ENDDA when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Current Byte Count Register of Channel 0
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURBC : PDMA Current Byte Count Register (Read Only)
This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BYTECNT register when PDMA is triggered or when a wraparound occurs
bits : 0 - 15 (16 bit)
access : read-only
PDMA Interrupt Enable Control Register of Channel 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXABTIEN : PDMA Read/Write Target Abort Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU whenever a PDMA transaction is aborted due to an error. If a transfer is aborted, PDMA channel must be reset to resume DMA operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA transfer target abort interrupt generation
#1 : 1
Enable PDMA transfer target abort interrupt generation
End of enumeration elements list.
TXOKIEN : PDMA Transfer Done Interrupt Enable
If enabled, the PDMA controller will generate and interrupt to the CPU when the requested PDMA transfer is complete.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PDMA transfer done interrupt generation
#1 : 1
Enable PDMA transfer done interrupt generation
End of enumeration elements list.
WAINTEN : Wraparound Interrupt Enable
If enabled, and channel source or destination address is in wraparound mode, the PDMA controller will generate a WRAP interrupt to the CPU according to the setting of
PDMA_DSCTn_CTL.WAINTSEL. This can be interrupts when the transaction has finished and has wrapped around and/or when the transaction is half way in progress. This allows the efficient implementation of circular buffers for DMA.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Wraparound PDMA interrupt generation
#1 : 1
Enable Wraparound interrupt generation
End of enumeration elements list.
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x204 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x208 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x20C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x210 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x214 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x218 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x21C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x220 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x224 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x234 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x238 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Interrupt Status Register of Channel 0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXABTIF : PDMA Read/Write Target Abort Interrupt Flag
This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again.
NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
TXOKIF : Block Transfer Done Interrupt Flag
This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer ongoing or Idle
#1 : 1
Transfer Complete
End of enumeration elements list.
WAIF : Wrap Around Transfer Byte Count Interrupt Flag
These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
0001 aaa Current transfer finished flag (CURBC aaaaaa 0).
0100 aaa Current transfer half complete flag (CURBC aaaaaa BYTECNT/2).
bits : 8 - 11 (4 bit)
access : read-write
INTSTS : Interrupt Pin Status (Read Only)
This bit is the Interrupt pin status of PDMA channel.
bits : 31 - 31 (1 bit)
access : read-only
address_offset : 0x300 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x304 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x308 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x30C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x310 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x314 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x318 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x31C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x320 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x324 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x334 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x338 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA Span Increment Register of Channel 0
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPANREG : Span Increment Register
This is a signed number in range [-128,127] for use in spanned address mode. If destination or source addressing mode is set as spanned, then this number is added to the address register each transfer. The size of the transfer is determined by the APB_TW setting. Note that span increment must be a multiple of the transfer width otherwise a memory addressing HardFault will occur. Also SPANREG may be a negative number.
bits : 0 - 8 (9 bit)
access : read-only
PDMA Current Span Increment Register of Channel 0
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSPANREG : Current Span Increment Register
This is a signed read only register for use in spanned address mode. It provides the current address offset from ENDSA or ENDDA if either is set to span mode.
bits : 0 - 15 (16 bit)
access : read-write
PDMA Transfer Source Address Register of Channel 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDSA : PDMA Transfer Source Address Register
This register holds the initial Source Address of PDMA transfer.
Note: The source address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Transfer Destination Address Register of Channel 0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENDDA : PDMA Transfer Destination Address Register
This register holds the initial Destination Address of PDMA transfer.
Note: The destination address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Transfer Byte Count Register of Channel 0
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTECNT : PDMA Transfer Byte Count Register
This register controls the transfer byte count of PDMA. Maximum value is 0xFFFF.
Note: When in memory-to-memory (PDMA_TXBCCHn.MODESEL aaa 00b) mode, the transfer byte count must be word aligned, that is multiples of 4bytes.
bits : 0 - 15 (16 bit)
access : read-write
CRC Control Register
address_offset : 0xE00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCEN : CRC Channel Enable
Setting this bit to 1 enables CRC's operation.
When operation in CRC DMA mode (TRGEN aaa 1), if user clears this bit, the DMA operation will be continuous until all CRC DMA operation is done, and the TRGEN bit will asserted until all CRC DMA operation done. But in this case, the PDMA_CRCINTF [TXOKIF] flag will inactive, user can read CRC result by reading PDMA_CRCCHKS register when TRGEN aaa 0
When operation in CRC DMA mode (TRGEN aaa 1), if user wants to stop the transfer immediately, user can write 1 to CRCRST bit to stop the transmission.
bits : 0 - 0 (1 bit)
access : read-write
CRCRST : CRC Engine Reset
Note: When operated in CPU PIO mode, setting this bit will reload the initial seed value.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will automatically be cleared after few clock cycles
End of enumeration elements list.
TRGEN : TRGEN
Note1: If this bit assert indicates the CRC engine operation in CRC DMA mode, do not fill in any data in PDMA_CRCDAT register.
Note2: When CRC DMA transfer is completed, this bit will be cleared automatically.
Note3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CRC DMA data read or write transfer Enabled
End of enumeration elements list.
DATREV : Write Data Order Reverse
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reversed for CRC write data in
#1 : 1
Bit order reversed for CRC write data in (per byte)
End of enumeration elements list.
CHKSREV : Checksum Reverse
Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reverse for CRC checksum
#1 : 1
Bit order reverse for CRC checksum
End of enumeration elements list.
DATFMT : Write Data Complement
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No 1's complement for CRC write data in
#1 : 1
1's complement for CRC write data in
End of enumeration elements list.
CHKSFMT : Checksum Complement
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No 1's complement for CRC checksum
#1 : 1
1's complement for CRC checksum
End of enumeration elements list.
DATLEN : CPU Write Data Length
When operation in CPU PIO mode (CRCEN aaa 1, TRGEN aaa 0), this field indicates the write data length.
00 aaa Data length is 8-bit mode
01 aaa Data length is 16-bit mode
1x aaa Data length is 32-bit mode
Note1: This field is used for CPU PIO mode.
Note2: When the data length is 8-bit mode, the valid data is PDMA_CRCDAT [7:0] if the data length is 16-bit mode, the valid data is PDMA_CRCDAT [15:0].
bits : 28 - 29 (2 bit)
access : read-write
CRCMODE : CRC Polynomial Mode
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
CRC-CCITT Polynomial mode
#01 : 1
CRC-8 Polynomial mode
#10 : 2
CRC-16 Polynomial mode
#11 : 3
CRC-32 Polynomial mode
End of enumeration elements list.
CRC DMA Source Address Register
address_offset : 0xE04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRCADDR : CRC DMA Transfer Source Address Register
This field indicates a 32-bit source address of CRC DMA.
Note: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write
CRC DMA Transfer Byte Count Register
address_offset : 0xE0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BYTECNT : CRC DMA Transfer Byte Count Register
This field indicates a 16-bit transfer byte count number of CRC DMA.
bits : 0 - 15 (16 bit)
access : read-write
CRC DMA Current Source Address Register
address_offset : 0xE14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURSA : CRC DMA Current Source Address Register (Read Only)
This field indicates the source address where the CRC DMA transfer just occurs.
bits : 0 - 31 (32 bit)
access : read-only
CRC DMA Current Transfer Byte Count Register
address_offset : 0xE1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURBC : CRC DMA Current Byte Count Register (Read Only)
This field indicates the current remained byte count of CRC_DMA.
Note: CRCRST will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only
CRC DMA Interrupt Enable Register
address_offset : 0xE20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXABTIEN : CRC DMA Read/Write Target Abort Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt generation Disabled during CRC DMA transfer
#1 : 1
Target abort interrupt generation Enabled during CRC DMA transfer
End of enumeration elements list.
TXOKIEN : CRC DMA Transfer Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generator Disabled when CRC DMA transfer is done
#1 : 1
Interrupt generator Enabled when CRC DMA transfer is done
End of enumeration elements list.
CRC DMA Interrupt Status Register
address_offset : 0xE24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXABTIF : CRC DMA Read/Write Target Abort Interrupt Flag
Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
TXOKIF : Block Transfer Done Interrupt Flag
This bit indicates that CRC DMA has finished all transfer.
Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not finished
#1 : 1
Done
End of enumeration elements list.
CRC Write Data Register
address_offset : 0xE80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRC Write Data Register
When operated in CPU PIO (PDMA_CRCCTL.CRCEN aaa 1, PDMA_CRCCTL.TRGEN aaa 0) mode, software can write data to this field to perform CRC operation
When operated in CRC DMA mode (PDMA_CRCCTL.CRCEN aaa 1, PDMA_CRCCTL.TRGEN aaa 0), this field will be used for DMA internal buffer.
Note1: When operated in CRC DMA mode, so don't filled any data in this field.
Note2: The PDMA_CRCCTL.DATFMT and PDMA_CRCCTL.DATREV bit setting will affect this field for example, if DATREV aaa 1, if the write data in PDMA_CRCDAT register is 0xAABBCCDD, the read data from PDMA_CRCDAT register will be 0x55DD33BB.
bits : 0 - 31 (32 bit)
access : read-write
CRC Seed Register
address_offset : 0xE84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEED : CRC Seed Register
This field indicates the CRC seed value.
bits : 0 - 31 (32 bit)
access : read-write
CRC Checksum Register
address_offset : 0xE88 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHECKSUM : CRC Checksum Register
This field indicates the CRC checksum.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Global Control Register
address_offset : 0xF00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWRST : PDMA Software Reset
Note: This bit can reset all channels (global reset).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles
End of enumeration elements list.
CHCKEN : PDMA Controller Channel Clock Enable Control
To enable clock for channel n CHCKEN[n] must be set.
CHCKEN[n] aaa 1: Enable Channel n clock
CHCKEN[n] aaa 0: Disable Channel n clock
bits : 8 - 11 (4 bit)
access : read-write
PDMA Service Selection Control Register
address_offset : 0xF04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIRXSEL : PDMA SPI0 Receive Selection
This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
bits : 0 - 3 (4 bit)
access : read-write
SPITXSEL : PDMA SPI0 Transmit Selection
This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
bits : 4 - 7 (4 bit)
access : read-write
ADCRXSEL : PDMA ADC Receive Selection
This field defines which PDMA channel is connected to ADC peripheral receive (PDMA source) request.
bits : 8 - 11 (4 bit)
access : read-write
DPWMTXSEL : PDMA DPWM Transmit Selection
This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
bits : 12 - 15 (4 bit)
access : read-write
UARTRXSEL : PDMA UART0 Receive Selection
This field defines which PDMA channel is connected to UART0 peripheral receive (PDMA source) request.
bits : 16 - 19 (4 bit)
access : read-write
UARTXSEL : PDMA UART0 Transmit Selection
This field defines which PDMA channel is connected to UART0 peripheral transmit (PDMA destination) request.
bits : 20 - 23 (4 bit)
access : read-write
I2SRXSEL : PDMA I2S Receive Selection
This field defines which PDMA channel is connected to I2S peripheral receive (PDMA source) request.
bits : 24 - 27 (4 bit)
access : read-write
I2STXSEL : PDMA I2S Transmit Selection
This field defines which PDMA channel is connected to I2S peripheral transmit (PDMA destination) request.
bits : 28 - 31 (4 bit)
access : read-write
PDMA Global Interrupt Status Register
address_offset : 0xF0C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GLOBALIF : Interrupt Pin Status (Read Only)
GLOBALIF[n] is the interrupt status of PDMA channel n.
bits : 0 - 3 (4 bit)
access : read-only
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