CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV (CLKDIV)

CLK_STATUS (STATUS)

CLK_PFLAG (PFLAG)

CLK_AHBCLK (AHBCLK)

CLK_APBCLK (APBCLK)

CLK_DPDFLR (DPDFLR)

FWK_EN : STOP/DeepSleep mode fast wakeup enable control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTL32K_EN : External 32.768 kHz Crystal Control After reset, this bit is 0 .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC49M_EN : Internal 49.152 MHz RC Oscillator Control After reset, this bit is 1 .
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTL32K_FILTER : Filter the XTL32K output clock Note 1: High level of XTL32K must keep 112 HCLK for recognition valid, when this bit is enabled. Note 2: Should be disabled when enter power down.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IO_FWK : All IO pin is enabled fast wakeup in STOP/DeepSleep mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOP : STOP mode bit. Set to '1' and issue WFI/WFE instruction to enter STOP mode.
bits : 9 - 9 (1 bit)
access : read-write

DEEP_PD : Deep Power Down (DPD) bit. Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 10 - 10 (1 bit)
access : read-write

OSC10K_EN : Internal 10kHz Oscillator Control After reset, this bit is 0 .
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VSET : Adjusts the digital supply voltage. Should be left as default .
bits : 13 - 15 (3 bit)
access : read-write

DPD_10K :
bits : 17 - 17 (1 bit)
access : read-write

FLASH_PWR : Determine whether FLASH memory enters deep power down. FLASH_PWR [0]: 1: flash enters deep power down upon DEEP_SLEEP FLASH_PWR [1]: 1: flash enters deep power down upon STOP mode. If FLASH_PWR is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence. Trade-off is wakeup time for standby power.
bits : 18 - 19 (2 bit)
access : read-write

TIMER_SEL : Select WAKEUP Timer:
bits : 20 - 23 (4 bit)
access : read-write

TIMER_WU : Read Only. This flag indicates that wakeup of device was requested with TIMER count of the 10Khz oscillator. Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC [10:8]) are cleared.
bits : 25 - 25 (1 bit)
access : read-write

TIMER_SEL_RD : Read-Only. Read back of the current WAKEUP timer setting. This value is updated with TIMER_SEL upon entering DPD mode.
bits : 28 - 31 (4 bit)
access : read-write

HCLKSEL : HCLK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STICKSEL : SYS_TICK Clock Source Select Note: 1. When power on, HIRC is selected as HCLK clock source. 2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FCLK_MUX_STATE : These register state shows the current HCLK is from which source clock Others reserved.
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCSEL : ADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : Timer0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1SEL : Timer1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2SEL : Timer2 Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMRFSEL : TimerF Clock Source Select
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCSEL : RTC Clock Source Select
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UARTSEL : UART Clock Source Select
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSCANSEL : CSCAN Clock Source Select
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0SEL : PWM Timer Clock Source Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1SEL : PWM Timer Clock Source Select
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UARTDIV : UART Clock Divide Number From HCLK Clock Source Note: UART engine clock must bigger or equal to HCLK.
bits : 4 - 7 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source The ADC engine clock must meet the constraint: ADCLK ( HCLK/2.
bits : 16 - 22 (7 bit)
access : read-write

LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRCSTB : HIRC clock source stable flag(Read only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DS_FLAG : Device has been in DEEP_SLEEP mode - write '1' to clear
bits : 0 - 0 (1 bit)
access : read-write

STOP_FLAG : Device has been in STOP mode - write '1' to clear.
bits : 1 - 1 (1 bit)
access : read-write

PDMACKEN : PDMA Clock Enable Control
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPIMCKEN : SPIM Clock Enable Control
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Control. The Flash ISP engine clock always is from 49 MHz RC oscillator.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UARTEN : UART Controller Clock Enable Control.(It works on APB)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_EN : Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-Time-Clock APB Interface Clock Control This bit is used to control the RTC APB clock only. The RTC engine clock source is from the LIRC and LXT (selected by RTCSEL (CLK_CLKSEL1 [24])).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMRF_EN : TimerF Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_EN : PWM0 Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1_EN : PWM1 Block Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Audio Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWM_EN : DPWM Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSCAN_EN : CSCAN clock enable control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_STATE : An 8bit register that is preserved when DPD (Deep Power Down) state is entered and after wakeup is available by reading PD_STATE_RB.
bits : 0 - 7 (8 bit)
access : read-write

PD_STATE_RB : Current values of PD_STATE register.
bits : 8 - 15 (8 bit)
access : read-write

VSET : Flash Regulator Voltage control. 0:1.8V, 1:2.4V, 2:2.5V, 3:2.7V, 4:3V, 5:3.3V, 6:1.5V, 7:1.7V
bits : 24 - 26 (3 bit)
access : read-write

PD : Flash Regulator Enable control. 0: Power Up Flash LDO regulator. 1: Power Down Flash LDO regulator. Note: When power down flash LDO and no external power at VCCB pin, the IO pull low discharge register(INT_BA+0x80 [7]) suggest to enable.
bits : 31 - 31 (1 bit)
access : read-write