PDMA_CSRx

PDMA_POINTx

PDMA_CSARx

PDMA_CDARx

PDMA_CBCRx

PDMA_IERx

PDMA_ISRx

PDMA_SARx

PDMA_DARx

PDMA_BCRx

CSAR : PDMA Current Source Address Register (Read Only) This register returns the source address from which the PDMA transfer is occurring. This register is loaded from SAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only

CDAR : PDMA Current Destination Address Register (Read Only) This register returns the destination address to which the PDMA transfer is occurring. This register is loaded from DAR when PDMA is triggered or when a wraparound occurs.
bits : 0 - 31 (32 bit)
access : read-only

CBCR : PDMA Current Byte Count Register (Read Only) This field indicates the current remaining byte count of PDMA transfer. This register is initialized with BCR register when PDMA is triggered or when a wraparound occurs
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IF : PDMA Read/Write Target Abort Interrupt Flag This flag indicates a Target Abort interrupt condition has occurred. This condition can happen if attempt is made to read/write from invalid or non-existent memory space. It occurs when PDMA controller receives a bus error from AHB master. Upon occurrence PDMA will stop transfer and go to idle state. To resume, software must reset PDMA channel and initiate transfer again. Note: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKD_IF : Block Transfer Done Interrupt Flag This bit indicates that PDMA block transfer complete interrupt has been generated. It is cleared by writing 1 to the bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAR_IF : Wrap around transfer byte count interrupt flag. These flags are set whenever the conditions for a wraparound interrupt (complete or half complete) are met. They are cleared by writing one to the bits.
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTR : Interrupt Pin Status (Read Only) This bit is the Interrupt pin status of PDMA channel.
bits : 31 - 31 (1 bit)
access : read-only

SAR : PDMA Transfer Source Address Register This register holds the initial Source Address of PDMA transfer. Note: The source address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write

DAR : PDMA Transfer Destination Address Register This register holds the initial Destination Address of PDMA transfer. Note: The destination address must be word aligned.
bits : 0 - 31 (32 bit)
access : read-write

POINT : PDMA Internal Buffer Pointer Register (Read Only) A PDMA transaction consists of two stages, a read from the source address and a write to the destination address. Internally this data is buffered in a 32bit register. If transaction width between the read and write transactions are different, this register tracks which byte/half-word of the internal buffer is being processed by the current transaction.
bits : 0 - 3 (4 bit)
access : read-only