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mem_usage : registers
protection :
Product Identifier Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG2 : Product Identifier
Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton.
bits : 0 - 15 (16 bit)
access : read-only
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Internal Oscillator Trim Register
address_offset : 0x110 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSC10K_TRIM : 23bit trim for 10kHz oscillator.
bits : 0 - 22 (23 bit)
access : read-write
TRM_CLK : Must be toggled to load a new OSC10K_TRIM
bits : 31 - 31 (1 bit)
access : read-write
10kHz oscillator and bias trim register
address_offset : 0x114 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Internal Oscillator Trim Register
address_offset : 0x118 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : 16bit sign extended representation of 10bit trim.
OSC_TRIM[0] maps to above-mentioned OSCTRIM.
OSC_TRIM[1] and OSC_TRIM[2] are reserved.
bits : 0 - 15 (16 bit)
access : read-write
EN2MHZ : 1: Low Frequency mode of oscillator active (2MHz).
0: High frequency mode (20-50MHz)
bits : 31 - 31 (1 bit)
access : read-write
Brown-out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write
PB1MFP : PB.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write
PB2MFP : PB.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write
PB3MFP : PB.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write
PB4MFP : PB.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write
PB5MFP : PB.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write
GPIO PA Multiple Alternate Functions and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PB Multiple Alternate Functions and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICE Multi-function-pin Controller Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ICE_EN : This bit will set ICE_CLK and ICE_DAT pins to be serial debug wires or PA.6/7
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE_CLK and ICE_DAT will be assigned as PA.6 and PA.7, for general IO purpose
#1 : 1
ICE_CLK and ICE_DAT will be set as ICE CLOCK/ ICE DIO, only for debugging purpose
End of enumeration elements list.
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR
#1 : 1
Power-on Reset (POR) Controller had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : RESETB Pin Reset Flag
The RESETB pin reset flag is set by the Reset Signal from the RESETB Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from RESETB pin
#1 : 1
Pin RESETB had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Watch-Dog
#1 : 1
The Watch-Dog module issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
BOD : BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown Out Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
BOD controller had issued the reset signal to reset the system
End of enumeration elements list.
PMURSTF : Reset Source From PMU
The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from PMU
#1 : 1
The PMU has issued the reset signal to reset the system
End of enumeration elements list.
PIN_WK : Wakeup from DPD From PIN
The device was woken from Deep Power Down by a low transition on the WAKEUP in or RESETB pin.
Note: Write 1 to this register to clear all wakeup flags.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from PIN
#1 : 1
The device was issued a wakeup from DPD by a pin transition
End of enumeration elements list.
TIM_WK : Wakeup from DPD From TIMER
The device was woken from Deep Power Down by count of 10kHz timer.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from TIMER
#1 : 1
The device was issued a wakeup from DPD by a TIMER event
End of enumeration elements list.
POR_WK : Wakeup from DPD From POR
The device was woken from Deep Power Down by a Power On Reset.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wakeup from POR
#1 : 1
The device was issued a wakeup from DPD by a POR
End of enumeration elements list.
GPIO Input Type and Slew Rate Ontrol
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA.15 ~ PA.0 Pull Resistance Control Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
PA.15 ~ PA.0 Digital and Analog Input Buffer Control Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB.5 ~ PB.0 Pull Resistance Control Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IEN :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Input buffer Enabled
#1 : 1
Input buffer disabled, and input signal always equals to 0
End of enumeration elements list.
PB.5 ~ PB.0 Digital Input Buffer Control Register
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IP Reset Control Resister0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles.
CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from Flash Memory are reloaded.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CHIP
End of enumeration elements list.
CPURST : CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CPU
End of enumeration elements list.
IP Reset Control Resister1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
TMRFRST : TimerF Controller Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
SPIMRST : SPIM Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
PWM1RST : PWM1 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
DPWMRST : DPWM Controller Reset
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
Reset
End of enumeration elements list.
MAP3 Data Image Register
address_offset : 0xF0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG3 : Data Image of MAP3
Data in MAP3 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
Device ID Register
address_offset : 0xF4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DEVICEID : Device ID Data
This register provides specific read-only information for the Device ID
bits : 0 - 15 (16 bit)
access : read-only
MAP0 Data Image Register
address_offset : 0xF8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG0 : Data Image of MAP0
Data in MAP0 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
MAP1 Data Image Register
address_offset : 0xFC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IMG1 : Data Image of MAP1
Data in MAP1 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only
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