\n

SCS

Peripheral Memory Blocks

address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x400 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

Registers

NVIC_ISER

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4


NVIC_ISER

IRQ0 ~ IRQ18 Set-enable Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER NVIC_ISER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set-Enable Bit The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34). Write Operation:
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ICER

IRQ0 ~ IRQ18 Clear-enable Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER NVIC_ICER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt Clear-Enable Bit The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34). Write Operation:
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt Disabled

1 : 1

Interrupt Disabled. Interrupt Enabled

End of enumeration elements list.


NVIC_ISPR

IRQ0 ~ IRQ18 Set-pending Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR NVIC_ISPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-Pending Bit The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34). Write Operation:
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Changes interrupt state to pending. Interrupt is pending

End of enumeration elements list.


NVIC_ICPR

IRQ0 ~ IRQ18 Clear-pending Control Register
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR NVIC_ICPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt Clear-Pending Bit The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34). Write Operation:
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : 0

No effect. Interrupt is not pending

1 : 1

Removes pending state of an interrupt. Interrupt is pending

End of enumeration elements list.


NVIC_IPR0

IRQ0 ~ IRQ3 Priority Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR0 NVIC_IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority Of IRQ0 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority Of IRQ1 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority Of IRQ2 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority Of IRQ3 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR1

IRQ4 ~ IRQ7 Priority Control Register
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR1 NVIC_IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6 PRI_7

PRI_4 : Priority Of IRQ4 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority Of IRQ5 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority Of IRQ6 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority Of IRQ7 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR2

IRQ8 ~ IRQ11 Priority Control Register
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR2 NVIC_IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_8 PRI_9 PRI_10 PRI_11

PRI_8 : Priority Of IRQ8 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority Of IRQ9 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority Of IRQ10 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority Of IRQ11 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR3

IRQ12 ~ IRQ15 Priority Control Register
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR3 NVIC_IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_12 PRI_13 PRI_14 PRI_15

PRI_12 : Priority Of IRQ12 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority Of IRQ13 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority Of IRQ14 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority Of IRQ15 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write


NVIC_IPR4

IRQ16 ~ IRQ18 Priority Control Register
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR4 NVIC_IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_12 PRI_13 PRI_14

PRI_12 : Priority Of IRQ12 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority Of IRQ13 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority Of IRQ14 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.