\n
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x400 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
IRQ0 ~ IRQ18 Set-enable Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set-Enable Bit
The NVIC_ISER register enables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ18 Clear-enable Control Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Clear-Enable Bit
The NVIC_ICER register disables interrupts, and shows what interrupts are enabled. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt Disabled
1 : 1
Interrupt Disabled.
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ18 Set-pending Control Register
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-Pending Bit
The NVIC_ISPR register forces interrupts into the pending state, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Changes interrupt state to pending.
Interrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ18 Clear-pending Control Register
address_offset : 0x280 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Interrupt Clear-Pending Bit
The NVIC_ICPR register removes the pending state of associated interrupts, and shows what interrupts are pending. Each bit represents an interrupt number from IRQ0 ~ IRQ18 (Vector number from 16 ~ 34).
Write Operation:
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
0 : 0
No effect.
Interrupt is not pending
1 : 1
Removes pending state of an interrupt.
Interrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ3 Priority Control Register
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority Of IRQ0
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority Of IRQ1
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority Of IRQ2
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority Of IRQ3
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Priority Control Register
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority Of IRQ4
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority Of IRQ5
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority Of IRQ6
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority Of IRQ7
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Priority Control Register
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority Of IRQ8
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority Of IRQ9
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority Of IRQ10
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority Of IRQ11
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Priority Control Register
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority Of IRQ15
0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write
IRQ16 ~ IRQ18 Priority Control Register
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority Of IRQ12
0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority Of IRQ13
0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority Of IRQ14
0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write
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