\n
address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
IRQ0 (WDT) Interrupt Source Identity Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ4 (SPIM) Interrupt Source Identity Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPIM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ5 (Timer0) Interrupt Source Identity Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ6 (Timer1) Interrupt Source Identity Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ7 (Timer2) Interrupt Source Identity Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ8 (GPA/B) Interrupt Source Identity Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: GPB_INT
Bit0: GPA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ9 (SPI0) Interrupt Source Identity Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ10 (PWM0) Interrupt Source Identity Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ11 (PDMA) Interrupt Source Identity Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ12 (TimerF) Interrupt Source Identity Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TimerF_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ13 (RTC) Interrupt Source Identity Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ15 (PWM1) Interrupt Source Identity Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ1 (DPWM) Interrupt Source Identity Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: DPWM_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ17 (UART) Interrupt Source Identity Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ18 (BOD) Interrupt Source Identity Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Source Interrupt Select
The NMI interrupt to Cortex-M0 can be selected from one of the interrupt [18:0].
The NMI_SEL bit is used to select the NMI interrupt source.
Note: IRQ3, IRQ14 and IRQ16 are reserved.
bits : 0 - 4 (5 bit)
access : read-write
IRQ_TM : IRQ Test Mode
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt register MCU_IRQ operates in normal mode. The MCU_IRQ collects all the interrupts from the peripheral and generates interrupt to MCU
#1 : 1
All the interrupts from peripheral to MCU are blocked. The peripheral IRQ signals (0-15) are replaced by the value in the MCU_IRQ register
End of enumeration elements list.
MCU IRQ Number Identify Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Test Mode
The MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to MCU Cortex-M0. There are two modes to generate interrupt to MCU Cortex-M0, the normal mode and test mode.
When MCU_IRQ[n] is 0 : Writing MCU_IRQ[n] 1 will generate an interrupt to Cortex_M0 IRQ[n].
When MCU_IRQ[n] is 1 (meaning an interrupt is asserted): Writing MCU_IRQ[n] 1 will clear the interrupt writing MCU_IRQ[n] 0 : has no effect.
Note: IRQ3, IRQ14 and IRQ16 are reserved.
bits : 0 - 15 (16 bit)
access : read-write
Reserved
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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