SPI0_CTL (CTL)

SPI0_RX0 (RX0)

SPI0_RX1 (RX1)

SPI0_TX0 (TX0)

SPI0_TX1 (TX1)

SPI_VARCLK

SPI_PDMACTL

SPI0_CLKDIV (CLKDIV)

SPI0_SSCTL (SSCTL)

GOBUSY : Go and Busy Status NOTE: All registers should be set before writing 1 to this BUSY bit. When a transfer is in progress, writing to any register of the SPI master/slave core has no effect.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXNET : Receive At Negative Edge
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXNEG : Transmit At Negative Edge
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DWIDTH : Transmit Bit Length This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted. DWIDTH aaa 0x01 --- 1 bit DWIDTH aaa 0x02 --- 2 bits ---- DWIDTH aaa 0x1f --- 31 bits DWIDTH aaa 0x00 --- 32 bits
bits : 3 - 7 (5 bit)
access : read-write

TXNUM : Transmit/Receive Word Numbers This field specifies how many transmit/receive word numbers should be executed in one transfer.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSB : LSB First
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

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CLKPOL : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPITV : Suspend Interval (Master Only) These four bits provide configurable suspend interval between two successive transmit/receive transactions in a transfer. The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL aaa 0. If CLKPOL aaa 1, the interval is from the rising clock edge to the falling clock edge. The default value is 0x0. When TXCNT aaa 00b, setting this field has no effect on transfer except as determined by REORDER[0] setting. The suspend interval is determined according to the following equation: (SUSPITV[3:0] + 2) * period of SCLK
bits : 12 - 15 (4 bit)
access : read-write

UNITIF : Interrupt Flag NOTE: This bit is cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

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UNITIEN : Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

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SLAVE : Master Slave Mode Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

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BYTEITV : Insert Sleep Interval Between Bytes This function is only valid for 32bit transfers (DWIDTH aaa 0). If set then a pause of (SUSPITV+2) SCLK cycles is inserted between each byte transmitted.
bits : 19 - 19 (1 bit)
access : read-write

REORDER : Byte Endian Reorder Function This function changes the order of bytes sent/received to be least significant physical byte first.
bits : 20 - 20 (1 bit)
access : read-write

FIFOEN : FIFO Mode
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VARCLKEN : Variable Clock Enable (Master Only) Note that when enabled, the setting of DWIDTH must be programmed as 0x10 (16 bits mode)
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEMPTY : Receive FIFO Empty Status
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

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RXFULL : Receive FIFO Full Status
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

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TXEMPTY : Transmit FIFO Empty Status
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFULL : Transmit FIFO Full Status
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMASSEN : Enable DMA Automatic SS function When enabled, interface will automatically generate a SS signal for an entire PDMA access transaction.
bits : 28 - 28 (1 bit)
access : read-write

RX : Data Receive Register The Data Receive Registers hold the value of received data of the last executed transfer. Valid bits depend on the transmit bit length field in the SPI_CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and Tx_NUM is set to 0x0, bit Rx0[7:0] holds the received data. NOTE: The Data Receive Registers are read only registers.
bits : 0 - 31 (32 bit)
access : read-only

Tx : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in the next transfer. Valid bits depend on the transmit bit length field in the CNTRL register. For example, if Tx_BIT_LEN is set to 0x08 and the Tx_NUM is set to 0x0, the bit Tx0[7:0] will be transmitted in next transfer. If Tx_BIT_LEN is set to 0x00 and Tx_NUM is set to 0x1, the core will perform two 32-bit transmit/receive successive using the same setting (the order is Tx0[31:0], Tx1[31:0]).
bits : 0 - 31 (32 bit)
access : write-only

VARCLK : Variable Clock Pattern The value in this field is the frequency pattern of the SPI clock. If the bit field of VARCLK is '0', the output frequency of SCLK is given by the value of DIVIDER. If the bit field of VARCLK is '1', the output frequency of SCLK is given by the value of DIVIDER2. Refer to register DIVIDER. Refer to Variable Serial Clock Frequency paragraph for detailed description.
bits : 0 - 31 (32 bit)
access : read-write

TXPDMAEN : Transmit DMA Start Set this bit to 1 will start the transmit DMA process. SPI module will issue request to DMA module automatically. If using DMA mode to transfer data, remember not to set GO_BUSY bit of SPI_CNTRL register. The DMA controller inside SPI module will set it automatically whenever necessary.
bits : 0 - 0 (1 bit)
access : read-write

RXPDMAEN : Receive DMA Start Set this bit to 1 will start the receive DMA process. SPI module will issue request to DMA module automatically.
bits : 1 - 1 (1 bit)
access : read-write

DIVIDER0 : Clock Divider Register (master only) The value in this field is the frequency division of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation: In other words, the maximum frequency of SCLK clock is one fifth of the SPI peripheral clock.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER1 : Clock Divider 2 Register (master only) The value in this field is the 2nd frequency divider of the system clock, PCLK, to generate the serial clock on the output SCLK. The desired frequency is obtained according to the following equation:
bits : 16 - 31 (16 bit)
access : read-write

SS : Slave Select Register (Master only) If AUTOSS bit is cleared, writing 1 to any bit location of this field sets the proper SPISSx0/1 line to an active state and writing 0 sets the line back to inactive state. If AUTOSS bit is set, writing 1 to any bit location of this field will select appropriate SPISSx0/1 line to be automatically driven to active state for the duration of the transmit/receive, and will be driven to inactive state for the rest of the time. (The active level of SPISSx0/1 is specified in SSACTPOL). Note: SPISSx0 is always defined as device/slave select input signal in slave mode.
bits : 0 - 1 (2 bit)
access : read-write

SSACTPOL : Slave Select Active Level It defines the active level of device/slave select signal (SPISSx0/1).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTOSS : Automatic Slave Select (Master only)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVTRGEN : Slave Select Level Trigger (Slave only)
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVTRGSTS : Level Trigger Flag When the LVTRGEN bit is set in slave mode, this bit can be read to indicate the received bit number is met the requirement or not. Note: This bit is READ only
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.