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TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x20 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x40 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

TIMER0_CTL

TIMER1_CTL

TIMER1_CMP

TIMER1_INTSTS

TIMER1_CNT

TIMERF_INTSTS

IR_CTL

TIMER0_CMP

TIMER2_CTL

TIMER2_CMP

TIMER2_INTSTS

TIMER2_CNT

TIMER0_INTSTS

TIMER0_CNT


TIMER0_CTL

Timer0 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CTL TIMER0_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC ACTSTS RSTCNT OPMODE INTEN CNTEN

PSC : Timer Clock Prescaler
bits : 0 - 7 (8 bit)
access : read-write

ACTSTS : Timer Active Status Bit (Read Only) This bit indicates the counter status of Timer.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

Timer is not active

#1 : 1

Timer is active

End of enumeration elements list.

RSTCNT : Counter Reset Bit Set this bit will reset the Timer counter, pre-scale and also force CNTEN to 0.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset Timer's pre-scale counter, internal 16-bit up-counter and CNTEN bit

End of enumeration elements list.

OPMODE : Timer Operating Mode
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

#00 : 0

The Timer is operating in the one-shot mode. The associated interrupt signal is generated once (if INTEN is 1) and CNTEN is automatically cleared by hardware

#01 : 1

The Timer is operating in the periodic mode. The associated interrupt signal is generated periodically (if INTEN is 1)

#10 : 2

Reserved

#11 : 3

The Timer is operating in continuous counting mode. The associated interrupt signal is generated when TIMERx_CNT = TIMERx_CMP (if INTEN is 1) however, the 16-bit up-counter counts continuously without reset

End of enumeration elements list.

INTEN : Interrupt Enable Bit If timer interrupt is enabled, the timer asserts its interrupt signal when the associated count is equal to TIMERx_CMP.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable TIMER Interrupt

#1 : 1

Enable TIMER Interrupt

End of enumeration elements list.

CNTEN : Counter Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

Stop/Suspend counting

#1 : 1

Start counting

End of enumeration elements list.


TIMER1_CTL

Timer1 Control and Status Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CTL TIMER1_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_CMP

Timer1 Compare Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CMP TIMER1_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_INTSTS

Timer1 Interrupt Status Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_INTSTS TIMER1_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER1_CNT

Timer1 Data Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER1_CNT TIMER1_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMERF_INTSTS

TimerF Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMERF_INTSTS TIMERF_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFIF TFIE

TFIF : TimerF Interrupt Flag This bit indicates the interrupt status of TimerF. TFIF bit is set by hardware when TimerF time out. It is cleared by writing 1 to this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

It indicates that TimerF does not time out yet

#1 : 1

It indicates that TimerF time out. The interrupt flag is set if TimerF interrupt was enabled

End of enumeration elements list.

TFIE : TimerF Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable TimerF Interrupt

#1 : 1

Enable TimerF Interrupt

End of enumeration elements list.


IR_CTL

IR Carrier Output Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR_CTL IR_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER0_CMP

Timer0 Compare Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CMP TIMER0_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPDAT

CMPDAT : Timer Comparison Value Note 1: Never set CMPDAT to 0x000 or 0x001. Timer will not function correctly. Note 2: No matter CNTEN is 0 or 1, whenever software writes a new value into this register, TIMER will restart counting by using this new value and abort previous count.
bits : 0 - 15 (16 bit)
access : read-write


TIMER2_CTL

Timer2 Control and Status Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CTL TIMER2_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_CMP

Timer2 Compare Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CMP TIMER2_CMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_INTSTS

Timer2 Interrupt Status Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_INTSTS TIMER2_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER2_CNT

Timer2 Data Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER2_CNT TIMER2_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER0_INTSTS

Timer0 Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_INTSTS TIMER0_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIF

TIF : Timer Interrupt Flag (Read Only) This bit indicates the interrupt status of Timer. TIF bit is set by hardware when the 16-bit counter matches the timer comparison value (CMPDAT). It is cleared by writing 1 to itself
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

No effect

#1 : 1

CNT (TIMERx_CNT[15:0]) value matches the CMPDAT (TIMERx_CMP[15:0]) value

End of enumeration elements list.


TIMER0_CNT

Timer0 Data Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CNT TIMER0_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Timer Data Register User can read this register for the current up-counter value while TIMERx_CTL.CNTEN is set to 1,
bits : 0 - 15 (16 bit)
access : read-only



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