DPWM_CTL (CTL)

DPWM_ZOHDIV (ZOHDIV)

DPWM_STS (STS)

DPWM_DMACTL (DMACTL)

DPWM_DATA (DATA)

MODUFRQ : DPWM Modulation Frequency.
bits : 0 - 2 (3 bit)
access : read-write

DEADTIME : DPWM Driver Deadtime Control. Enabling this bit will insert an additional clock cycle deadtime into the switching of PMOS and NMOS driver transistors.
bits : 3 - 3 (1 bit)
access : read-write

DITHEREN : DPWM Signal Dither Control To prevent structured noise on PWM output due to DC offsets in the input signal it is possible to add random dither to the PWM signal. These bits control the dither: 0: No dither. 1: ±1 bit dither 3: ±2 bit dither
bits : 4 - 5 (2 bit)
access : read-write

DPWMEN : DPWM Enable. 1: Enable DPWM, SPK pins are enabled and driven, data is taken from FIFO. 0: Disable DPWM, SPK pins are tri-state, CIC filter is reset, FIFO pointers are reset (FIFO data is not reset). Note : This field will be effective only when DAC_EN field in this register is set as 0 .
bits : 6 - 6 (1 bit)
access : read-write

CLIPIE : Read data in DATA[31:0] clipped within 0x0000-7fff ~ 0xffff-8000 Read operation of this register will get clipped data in DATA[31:0] register but clipped with the range : 0x00 ~ 7fff ~ 0x ffff ~8000. The content of DATA[31:0] will not be change.
bits : 7 - 7 (1 bit)
access : read-write

RXTHIE : DPWM FIFO threshold interrupt 1: DPWM FIFO threshold interrupt Enabled. 0: DPWM FIFO threshold interrupt Disabled.
bits : 8 - 8 (1 bit)
access : read-write

RXTH : DPWM FIFO threshold If the valid data count of the DPWM FIFO buffer is less than or equal to RXTH setting, the RXTHF bit will set to 1, else the RXTHF bit will be cleared to 0.
bits : 9 - 12 (4 bit)
access : read-write

ZCIE : Zero cross enable 0: output data doesn't cross zero point 1: output data cross zero point
bits : 14 - 14 (1 bit)
access : read-write

DAC_EN : DAC ENABLE 0 --- DAC function disable 1 --- DAC function enable
bits : 16 - 16 (1 bit)
access : read-write

DAC_EN_10BIT : DAC ENABLE 10Bit 0 --- 13 Bit mode 1 --- 10 bit mode, don't use lower 3BITs
bits : 17 - 17 (1 bit)
access : read-write

DAC_PD : DAC POWER DOWN 0 --- power on DAC13B 1 --- power down DAC13B
bits : 18 - 18 (1 bit)
access : read-write

DACBUFBYPASS : DAC BUFFER BYPASS 0 --- disable BYPASS DAC BUFFER 1 --- enable BYPASS DAC BUFFER
bits : 19 - 19 (1 bit)
access : read-write

DACBUF_PD : DAC BUFFER POWER DOWN 0 --- power on DAC BUFFER 1 --- power off DAC BUFFER
bits : 20 - 20 (1 bit)
access : read-write

DAC_INSEL : DAC input data selection 0 --- DATA from CIC and GAIN output 1 --- DATA from FIFO output
bits : 21 - 21 (1 bit)
access : read-write

ZOH_DIV : DPWM Zero Order Hold, down-sampling divisor. The input sample rate of the DPWM is set by HCLK frequency and the divisor set in this register by the following formula: Valid range is 1,..,255. Default is 48, which gives a sample rate of 16kHz for a 49.152MHz (default) HCLK.
bits : 0 - 7 (8 bit)
access : read-write

GAIN : (GAIN[7:0]+1)/256, GAIN≠0
bits : 8 - 15 (8 bit)
access : read-write

DAC_DIV : DAC clock divider DAC data sample rate is set by this divider
bits : 16 - 21 (6 bit)
access : read-write

FULL : FIFO Full
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

EMPTY : FIFO Empty
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTHF : DPWM FIFO threshold Interrupt Status (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FIFO_POINTER : DPWM FIFO Pointer (Read Only) The FULL bit and FIFO_POINTER[3:0] indicates the field that the valid data count within the DPWM FIFO buffer. The Maximum value shown in FIFO_POINTER is 15. When the using level of DPWM FIFO Buffer equal to 16, The FULL bit is set to 1.
bits : 3 - 6 (4 bit)
access : read-only

DMAEN : Enable DPWM and DAC DMA Interface.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INDATA : DPWM and DAC FIFO Audio Data Input A write to this register pushes data onto the DPWM and DAC FIFO and increments the write pointer. This is the address that PDMA writes audio data to.
bits : 0 - 15 (16 bit)
access : write-only