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PDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

PDMA_GCRCSR

PDMA_PDSSR

PDMA_GCRISR


PDMA_GCRCSR

PDMA Global Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRCSR PDMA_GCRCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDMA_RST HCLK_EN

PDMA_RST : PDMA Software Reset Note: This bit can reset all channels (global reset).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Writing 0 to this bit has no effect

#1 : 1

Writing 1 to this bit will reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will auto clear after several clock cycles

End of enumeration elements list.

HCLK_EN : PDMA Controller Channel Clock Enable Control To enable clock for channel n HCLK_EN[n] must be set.
bits : 8 - 9 (2 bit)
access : read-write


PDMA_PDSSR

PDMA Service Selection Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDMA_PDSSR PDMA_PDSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0_RXSEL SPI0_TXSEL SPIM_RXSEL SPIM_TXSEL DPWM_TXSEL

SPI0_RXSEL : PDMA SPI0 Receive Selection This field defines which PDMA channel is connected to SPI0 peripheral receive (PDMA source) request.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

No channel select

#01 : 1

Select channel 0

#10 : 2

Select channel 1

#11 : 3

Reserved

End of enumeration elements list.

SPI0_TXSEL : PDMA SPI0 Transmit Selection This field defines which PDMA channel is connected to SPI0 peripheral transmit (PDMA destination) request.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

No channel select

#01 : 1

Select channel 0

#10 : 2

Select channel 1

#11 : 3

Reserved

End of enumeration elements list.

SPIM_RXSEL : PDMA SPIM Receive Selection This field defines which PDMA channel is connected to SPIM peripheral receive (PDMA source) request.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

No channel select

#01 : 1

Select channel 0

#10 : 2

Select channel 1

#11 : 3

Reserved

End of enumeration elements list.

SPIM_TXSEL : PDMA SPIM Transmit Selection This field defines which PDMA channel is connected to SPIM peripheral transmit (PDMA destination) request.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

#00 : 0

No channel select

#01 : 1

Select channel 0

#10 : 2

Select channel 1

#11 : 3

Reserved

End of enumeration elements list.

DPWM_TXSEL : PDMA DPWM Transmit Selection This field defines which PDMA channel is connected to DPWM peripheral transmit (PDMA destination) request.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

#00 : 0

No channel select

#01 : 1

Select channel 0

#10 : 2

Select channel 1

#11 : 3

Reserved

End of enumeration elements list.


PDMA_GCRISR

PDMA Global Interrupt Status Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PDMA_GCRISR PDMA_GCRISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCRISR

GCRISR : Interrupt Pin Status (Read Only) GCRISR[n] is the interrupt status of PDMA channel n.
bits : 0 - 1 (2 bit)
access : read-only



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