Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :
Control and Status Register 0
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDMAEN : RX DMA Enable Control Bit
If set RXDMAEN to high, SPI interface will receive the data from slave automatically.
Note: Only support master mode.
Note2: Before setting RXDMAEN, user must set PDMA register correctly first.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA Disabled
#1 : 1
DMA Enable
End of enumeration elements list.
TXDMAEN : TX DMA Enable Control Bit
If set TXDMAEN to high, SPI interface will transfer the data to slave automatically.
Note: Only support master mode.
Note2: Before setting RXDMAEN, user must set PDMA register correctly first.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA Disabled
#1 : 1
DMA Enable
End of enumeration elements list.
IEN : Interrupt Enable Control
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM Interrupt Disabled
#1 : 1
SPIM Interrupt Enabled
End of enumeration elements list.
IF : Interrupt Flag
Write Operation:
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
The transfer has not finished yet
#1 : 1
Write 1 to clear.
The transfer has done
End of enumeration elements list.
DWIDTH : Transmit/Receive Bit Length
This field specifies how many bits are transmitted/received in one transmit/receive transaction.
Note: Only 8-, 16-, 24-, and 32-bit are allowed. Other bit length will result in incorrect transfer.
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0x7 : 7
8 bits
0xf : 15
16 bits
0x17 : 23
24 bits
0x1f : 31
32 bits
End of enumeration elements list.
BURSTNUM : Transmit/Receive Burst Number
This field specifies how many transmit/receive transactions should be executed continuously in one transfer.
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive transaction will be executed in one transfer
#01 : 1
Two successive transmit/receive transactions will be executed in one transfer
#10 : 2
Three successive transmit/receive transactions will be executed in one transfer
#11 : 3
Four successive transmit/receive transactions will be executed in one transfer
End of enumeration elements list.
QDIODIR : SPI Interface Direction Select For Quad/Dual Mode
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interface signals are input
#1 : 1
Interface signals are output
End of enumeration elements list.
SUSPITV : Suspend Interval
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : 0
2 HCLK clock cycles
0x1 : 1
3 HCLK clock cycles
0xe : 14
16 HCLK clock cycles
0xf : 15
17 HCLK clock cycles
End of enumeration elements list.
BITMODE : SPI Interface Bit Mode
Note. SPIM_MOSI is Data 0 pin for Quad Mode.
SPIM_MISO is Data 1 pin for Quad Mode.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Standard mode
#01 : 1
Dual mode
#10 : 2
Quad mode
#11 : 3
Reserved
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
The Data Receive Registers hold the received data of the last executed transfer.
Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM > 0, received data are held in the most significant RX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RX register first.
In a byte, received data are held in the most significant bit of RX register first.
bits : 0 - 31 (32 bit)
access : read-only
Data Receive Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Receive Register 2
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Receive Register 3
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
The Data Transmit Registers hold the data to be transmitted in next transfer.
Number of valid TX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM > 0, data are transmitted in the most significant TX register first.
Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TX register first.
In a byte, data are transmitted in the most significant bit of TX register first.
bits : 0 - 31 (32 bit)
access : read-write
Data Transmit Register 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 3
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Control Register 1
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIMEN : Go and Busy Status
Write Operation:
Note: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, you should not write to any register of this peripheral.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.
The transfer has done
#1 : 1
Start the transfer. This bit remains set during the transfer and is automatically cleared after transfer finished.
The transfer has not finished yet
End of enumeration elements list.
SS : Slave Select Active Enable Control
Note: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPIM_SS is in active level
#1 : 1
SPIM_SS is in inactive level
End of enumeration elements list.
SSACTPOL : Slave Select Active Level
It defines the active level of device/slave select signal (SPIM_SS).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPIM_SS slave select signal is Active Low
#1 : 1
The SPIM_SS slave select signal is Active High
End of enumeration elements list.
DLYSEL : RX Sample Clock Source Delay Chain Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Not Delay
#001 : 1
Select sample clock through 2 Delay Cell
#010 : 2
Select sample clock through 4 Delay Cell
#011 : 3
Select sample clock through 6 Delay Cell
#111 : 7
Select sample clock through 14 Delay Cell
End of enumeration elements list.
DIVIDER : Clock Divider Register
The value in this field is the frequency divider of the system clock to generate the serial clock on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation:
Note: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of SYS_CLK.
bits : 16 - 31 (16 bit)
access : read-write
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