\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection :
UART0 Receive/Transmit FIFO Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART0 Modem Control Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTS : RTS (Request-to-send) Signal
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Drive RTS inactive ( = ~RTSACTLV)
#1 : 1
Drive RTS active ( = RTSACTLV)
End of enumeration elements list.
LBMEN : Loopback Mode Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RTSACTLV : Request-to-send (RTS) Active Trigger Level
This bit can change the RTS trigger level.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTS is active low level
#1 : 1
RTS is active high level
End of enumeration elements list.
RTSSTS : RTS Pin State (Read Only)
This bit is the pin status of RTS.
bits : 13 - 13 (1 bit)
access : read-only
UART0 Modem Status Register.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTSDETF : Detect CTS State Change Flag
NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
CTSSTS : CTS Pin Status (Read Only)
This bit is the pin status of CTS.
bits : 4 - 4 (1 bit)
access : read-only
CTSACTLV : Clear-to-send (CTS) Active Trigger Level
This bit can change the CTS trigger level.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
CTS is active low level
#1 : 1
CTS is active high level
End of enumeration elements list.
UART0 FIFO Status Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOVIF : Rx Overflow Error Interrupt Flag
If the Rx FIFO (UART_DAT) is full, and an additional byte is received by the UART, an overflow condition will occur and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write
PEF : Parity Error Flag
This bit is set to logic 1 whenever the received character does not have a valid parity bit , and is reset whenever the CPU writes 1 to this bit.
bits : 4 - 4 (1 bit)
access : read-write
FEF : Framing Error Flag
This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
bits : 5 - 5 (1 bit)
access : read-write
BIF : Break Interrupt Flag
This bit is set to a logic 1 whenever the receive data input (Rx) is held in the space state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). It is reset whenever the CPU writes 1 to this bit.
bits : 6 - 6 (1 bit)
access : read-write
RXPTR : Rx FIFO Pointer (Read Only)
This field returns the Rx FIFO buffer pointer. It is the number of bytes available for read in the Rx FIFO. When UART receives one byte from external device, RXPTR is incremented. When one byte of Rx FIFO is read by CPU, RXPTR is decremented.
bits : 8 - 13 (6 bit)
access : read-only
RXEMPTY : Receive FIFO Empty (Read Only)
This bit indicates whether the Rx FIFO is empty or not.
When the last byte of Rx FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only
RXFULL : Receive FIFO Full (Read Only)
This bit indicates whether the Rx FIFO is full or not.
This bit is set when Rx FIFO is full otherwise it is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only
TXPTR : Tx FIFO Pointer (Read Only)
This field returns the Tx FIFO buffer pointer. When CPU writes a byte into the Tx FIFO, TXPTR is incremented. When a byte from Tx FIFO is transferred to the Transmit Shift Register, TXPTR is decremented.
bits : 16 - 21 (6 bit)
access : read-only
TXEMPTY : Transmit FIFO Empty (Read Only)
This bit indicates whether the Tx FIFO is empty or not.
When the last byte of Tx FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared after writing data to FIFO (Tx FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only
TXFULL : Transmit FIFO Full (Read Only)
This bit indicates whether the Tx FIFO is full or not.
bits : 23 - 23 (1 bit)
access : read-only
TXOVIF : Tx Overflow Error Interrupt Flag
If the Tx FIFO (UART_DAT) is full, an additional write to UART_DAT will cause an overflow condition and set this bit to logic 1. It will also generate a BUFERRIF event and interrupt if enabled.
NOTE: This bit is cleared by writing 1 to itself.
bits : 24 - 24 (1 bit)
access : read-write
TXEMPTYF : Transmitter Empty (Read Only)
Bit is set by hardware when Tx FIFO is empty and the STOP bit of the last byte has been transmitted.
Bit is cleared automatically when Tx FIFO is not empty or the last byte transmission has not completed.
NOTE: This bit is read only.
bits : 28 - 28 (1 bit)
access : read-only
UART0 Interrupt Status Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIF : Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the Rx FIFO equals UART_FIFO.RFITL then the RDAIF will be set. If UART_INTEN.RDAIEN is enabled, the RDA interrupt will be generated.
NOTE: This bit is read only and it will be cleared when the number of unread bytes of Rx FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only
THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of Tx FIFO is transferred to Transmitter Shift Register. If UART_INTEN.THREIEN is enabled, the THRE interrupt will be generated.
NOTE: This bit is read only and it will be cleared when writing data into the Tx FIFO.
bits : 1 - 1 (1 bit)
access : read-only
RLSIF : Receive Line Status Interrupt Flag (Read Only)
This bit is set when the Rx receive data has a parity, framing or break error (at least one of, UART_FIFOSTS.BIF, UART_FIFOSTS.FEF and UART_FIFOSTS.PEF, is set). If UART_INTEN.RLSIEN is enabled, the RLS interrupt will be generated.
NOTE: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
bits : 2 - 2 (1 bit)
access : read-only
MODENIF : MODEM Interrupt Flag (Read Only)
NOTE: This bit is read only and reset when bit UART_MODEMSTS.CTSDETF is cleared by a write 1.
bits : 3 - 3 (1 bit)
access : read-only
RXTOIF : Time Out Interrupt Flag (Read Only)
This bit is set when the Rx FIFO is not empty and no activity occurs in the Rx FIFO and the time out counter equal to TOIC. If UART_INTEN.TOUT_IEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is read only and user can read FIFO to clear it.
bits : 4 - 4 (1 bit)
access : read-only
BUFERRIF : Buffer Error Interrupt Flag (Read Only)
This bit is set when either the Tx or Rx FIFO overflows (UART_FIFOSTS.TXOVIF or UART_FIFOSTS.RXOVIF is set). When BUFERRIF is set, the serial transfer may be corrupted. If UART_INTEN.BUFERRIEN is enabled a CPU interrupt request will be generated.
NOTE: This bit is cleared when both UART_FIFOSTS.TXOVIF and UART_FIFOSTS.RXOVIF are cleared.
bits : 5 - 5 (1 bit)
access : read-only
RDAINT : Receive Data Available Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RDAIEN and RDAIF.
bits : 8 - 8 (1 bit)
access : read-write
THERINT : Transmit Holding Register Empty Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.THREIEN and THREIF.
bits : 9 - 9 (1 bit)
access : read-write
RLSINT : Receive Line Status Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RLSIEN and RLSIF.
bits : 10 - 10 (1 bit)
access : read-write
MODEMINT : MODEM Status Interrupt Indicator to Interrupt
Logical AND of UART_INTEN.MODEMIEN and MODENIF.
bits : 11 - 11 (1 bit)
access : read-write
RXTOINT : Time Out Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.RXTOIEN and RXTOIF.
bits : 12 - 12 (1 bit)
access : read-write
BUFERRINT : Buffer Error Interrupt Indicator to Interrupt Controller
Logical AND of UART_INTEN.BUFERRIEN and BUFERRIF.
bits : 13 - 13 (1 bit)
access : read-write
UART0 Time Out Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRD : Baud Rate Divider. Refer to Table 510 for more information.
bits : 0 - 15 (16 bit)
access : read-write
EDIVM1 : Divider x
bits : 24 - 27 (4 bit)
access : read-write
BAUDM0 : Divider X Equal 1
Refer to Table 5116 UART Baud Rate Setting Table for more information.
bits : 28 - 28 (1 bit)
access : read-write
BAUDM1 : Divider X Enable
Refer to Table 5116 UART Baud Rate Setting Table for more information.
NOTE: When in IrDA mode, this bit must disabled.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable divider X ( M = 16)
#1 : 1
Enable divider X (M = EDIVM1+1, with EDIVM1 ≥ 8)
End of enumeration elements list.
UART0 Baud Rate Divisor Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UART IrDA Control Register.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEN : Transmit/Receive Selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Enable IrDA receiver
#1 : 1
Enable IrDA transmitter
End of enumeration elements list.
LOOPBACK : IrDA Loopback Test Mode
Loopback Tx to Rx.
bits : 2 - 2 (1 bit)
access : read-write
TXINV : Transmit Inversion Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No inversion
#1 : 1
Invert Tx output signal
End of enumeration elements list.
RXINV : Receive Inversion Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No inversion
#1 : 1
Invert Rx input signal
End of enumeration elements list.
UART LIN Control Register.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKFL : UART LIN Break Field Length Count
This field indicates a 4-bit LIN Tx break field count.
NOTE: This break field length is BRKFL + 2
bits : 0 - 3 (4 bit)
access : read-write
LINRXEN : LIN RX Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable LIN Rx mode
#1 : 1
Enable LIN Rx mode
End of enumeration elements list.
LINTXEN : LIN TX Break Mode Enable
NOTE: When Tx break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable LIN Tx Break Mode
#1 : 1
Enable LIN Tx Break Mode
End of enumeration elements list.
UART Function Select Register.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LINEN : Enable LIN Function
Note that IrDA and LIN functions are mutually exclusive: both cannot be active at same time.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART Function
#1 : 1
Enable LIN Function
End of enumeration elements list.
IRDAEN : Enable IrDA Function
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART Function
#1 : 1
Enable IrDA Function
End of enumeration elements list.
UART0 Interrupt Enable Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDAIEN : Receive Data Available Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RDAINT
#1 : 1
Enable RDAINT
End of enumeration elements list.
THREIEN : Transmit FIFO Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off THERINT
#1 : 1
Enable THERINT
End of enumeration elements list.
RLSIEN : Receive Line Status Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RLSINT
#1 : 1
Enable RLSINT
End of enumeration elements list.
MODEMIEN : Modem Status Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off MODEMINT
#1 : 1
Enable MODEMINT
End of enumeration elements list.
RXTOIEN : Receive Time Out Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off RXTOINT
#1 : 1
Enable RXTOINT
End of enumeration elements list.
BUFERRIEN : Buffer Error Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Mask off BUFERRINT
#1 : 1
Enable IBUFERRINT
End of enumeration elements list.
TOCNTEN : Time-out Counter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable Time-out counter
#1 : 1
Enable
End of enumeration elements list.
ATORTSEN : RTS Auto Flow Control Enable
When RTS auto-flow is enabled, if the number of bytes in the Rx FIFO equals UART_FIFO.RTSTRGLV, the UART will de-assert the RTS signal.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable RTS auto flow control
#1 : 1
Enable
End of enumeration elements list.
ATOCTSEN : CTS Auto Flow Control Enable
When CTS auto-flow is enabled, the UART will send data to external device when CTS input is asserted (UART will not send data to device until CTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CTS auto flow control
#1 : 1
Enable
End of enumeration elements list.
UART0 FIFO Control Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRST : Receive FIFO Reset
When RXRST is set, all the bytes in the receive FIFO are cleared and receive internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the receiving internal state machine and pointers
End of enumeration elements list.
TXRST : Transmit FIFO Reset
When TXRST is set, all the bytes in the transmit FIFO are cleared and transmit internal state machine is reset.
Note: This bit will auto-clear after 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the transmit internal state machine and pointers
End of enumeration elements list.
RFITL : Receive FIFO Interrupt (RDAINT) Trigger Level
bits : 4 - 7 (4 bit)
access : read-write
RTSTRGLV : RTS Trigger Level for Auto-flow Control
bits : 16 - 19 (4 bit)
access : read-write
UART0 Line Control Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLS : Word Length Select
bits : 0 - 1 (2 bit)
access : read-write
NSB : Number of STOP bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
One STOP bit is generated after the transmitted data
#1 : 1
Two STOP bits are generated when 6-, 7- and 8-bit word length is selected One and a half STOP bits are generated in the transmitted data when 5-bit word length is selected
End of enumeration elements list.
PBE : Parity Bit Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Parity bit is not generated (transmit data) or checked (receive data) during transfer
#1 : 1
Parity bit is generated or checked between the last data word bit and stop bit of the serial data
End of enumeration elements list.
EPE : Even Parity Enable
This bit has effect only when PBE (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's are transmitted or checked in the data word and parity bits
#1 : 1
Even number of logic 1's are transmitted or checked in the data word and parity bits
End of enumeration elements list.
SPE : Stick Parity Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable stick parity
#1 : 1
When bits PBE and SPE are set 'Stick Parity' is enabled. If EPE=0 the parity bit is transmitted and checked as always set, if EPE=1, the parity bit is transmitted and checked as always cleared
End of enumeration elements list.
BCB : Break Control Bit
When this bit is set to logic 1, the serial data output (Tx) is forced to the 'Space' state (logic 0). Normal condition is serial data output is 'Mark' state. This bit acts only on Tx and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write
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