\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable ISP function
#1 : 1
Enable ISP function
End of enumeration elements list.
BS : Boot Select
1: LDROM, 0: APROM
Modify this bit to select which ROM next boot is to occur. This bit also functions as MCU boot status flag, which can be used to check where MCU booted from. This bit is initialized after power-on reset with the inverse of CBS in Config0 It is not reset for any other reset event.
bits : 1 - 1 (1 bit)
access : read-write
CFGUEN : CONFIG Update Enable
When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#1 : 1
Enable, 0 = Disable
End of enumeration elements list.
LDUEN : LDROM Update Enable
LDROM update enable bit.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated when the MCU runs in APROM
End of enumeration elements list.
ISPFF : ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) Destination address is illegal, such as over an available range.
Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write
SWRST : Software Reset
Writing 1 to this bit will initiate a software reset. It is cleared by hardware after reset.
bits : 7 - 7 (1 bit)
access : read-write
WAIT_CFG : Flash Access Wait State Configuration
0x11: Zero wait states. HCLK < 24MHz
0x01: Two wait states.
0x00: Four wait state.
Before changing WAIT_CFG, ensure HCLK speed is < 25MHz.
bits : 16 - 18 (3 bit)
access : read-write
CACHE_DIS : Cache Disable
When set to 1, caching of flash memory reads is disabled.
bits : 21 - 21 (1 bit)
access : read-write
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger
Write 1 to start ISP operation. This will be cleared to 0 by hardware automatically when ISP operation is finished.
After triggering an ISP function M0 instruction pipeline should be flushed with a ISB instruction to guarantee data integrity.
This is a protected register, user must first follow the unlock sequence (see Register Lock Control Register (SYS_REGLCTL)) to gain access.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is on going
End of enumeration elements list.
Data Flash Base Address Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBA : Data Flash Base Address
This register reports the data flash starting address. It is a read only register.
Data flash size is defined by user configuration, register content is loaded from Config1 when chip is reset.
bits : 0 - 31 (32 bit)
access : read-only
ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADR : ISP Address Register
This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32bit words only, consequently ISPARD[1:0] must be 00b for correct ISP operation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data Register
Write data to this register before an ISP program operation.
Read data from this register after an ISP read operation
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPCMD : ISP Command
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0x00 : 0
Read
0x0b : 11
Read CID
0x0c : 12
Read DID
0x21 : 33
Program
0x22 : 34
Page Erase
End of enumeration elements list.
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