ADC_DAT0 (DAT0)

ADC_DAT4 (DAT4)

ADC_DAT5 (DAT5)

ADC_DAT6 (DAT6)

ADC_DAT7 (DAT7)

ADC_CTL (CTL)

ADC_CHSEQ (CHSEQ)

ADC_CMP0 (CMP0)

ADC_CMP1 (CMP1)

ADC_STATUS (STATUS)

ADC_PDMADAT (PDMADAT)

ADC_PGCTL (PGCTL)

ADC_DAT1 (DAT1)

ADC_VMID (VMID)

ADC_HWPARA (HWPARA)

ADC_DAT2 (DAT2)

ADC_DAT3 (DAT3)

RESULT : A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
bits : 0 - 11 (12 bit)
access : read-only

EXTS : Extension Bits Of RESULT for Different Data Format If ADCFM is '0', EXTS all are read as '0'. If ADCFM is '1', EXTS all are read as bit RESULT [11].
bits : 12 - 15 (4 bit)
access : read-only

OV : Over Run Flag If converted data in RESULT [11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADCEN : A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIE : A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : A/D Converter Operation Mode Note 1: This field will be effective only when DS_EN field in this register is set as '0'. When DS_EN is set as '1', ADC conversion will be forced to 'continuous scan mode' Note 2: When changing the operation mode, software should disable SWTRG bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMAEN : PDMA Transfer Enable Bit When A/D conversion is completed, the converted data is loaded into ADC_DATn (n: 0 ~ 7) register, user can enable this bit to generate a PDMA data transfer request.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D Conversion Start Note1: SWTRG bit can be reset to 0 by software, or can be cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets. Note2: Before trigger SWTRG to start ADC convert , the ADC relative setting should be completed.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCFM : Data Format Of ADC Conversion Result
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DS_RATE : Down Sample Rate
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DS_1CH :
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DS_EN : Down Sample Function Enable
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HP_FSEL : High-pass Filter Frequency Selection:
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HP_EN : High-pass Filter Enable Note: HP_EN suggest to be used only when DS_EN enable.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHSEQ0 : Select Channel N As The 1st Conversion In Scan Sequence
bits : 0 - 3 (4 bit)
access : read-write

CHSEQ1 : Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 4 - 7 (4 bit)
access : read-write

CHSEQ2 : Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 8 - 11 (4 bit)
access : read-write

CHSEQ3 : Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 12 - 15 (4 bit)
access : read-write

CHSEQ4 : Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 16 - 19 (4 bit)
access : read-write

CHSEQ5 : Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 20 - 23 (4 bit)
access : read-write

CHSEQ6 : Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 24 - 27 (4 bit)
access : read-write

CHSEQ7 : Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 28 - 31 (4 bit)
access : read-write

ADCMPEN : Compare Enable Set this bit to 1 to enable the comparison CMPDAT with specified channel conversion result when converted data is loaded into ADC_DAT register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPIE : Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT, ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPMCNT : Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Compare Data This field possessing the 5 MSB of 12-bit compare data, and 7 LSB are treated as '0', is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit.
bits : 23 - 27 (5 bit)
access : read-write

ADIF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP0, then this bit is set to 1. And it is cleared by write 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCMPF1 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP1, then this bit is set to 1. And it is cleared by write 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE This bit is mirror of SWTRG bit in ADC_CTL. It is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel It is read only.
bits : 4 - 6 (3 bit)
access : read-write

VALID : Data Valid Flag It is a mirror of VALID bit in ADC_DATn.
bits : 8 - 15 (8 bit)
access : read-write

OV : Over Run Flag It is a mirror to OV bit in ADC_DATn.
bits : 16 - 23 (8 bit)
access : read-write

PDMA_RESULT : ADC PDMA transfer data If DS_EN is '0' and HPF_EN is '0', transfer SAR output to SRAM If DS_EN is '1' and HPF_EN is '0', transfer DS output to SRAM If HPF_EN is '1', transfer HPF output to SRAM
bits : 0 - 15 (16 bit)
access : read-write

MUTE_PGA : PGA mute/unmute control 0: UNMUTE PGA 1: MUTE PGA
bits : 0 - 0 (1 bit)
access : read-write

ZERO_CROSS : Zero cross enable control 0: immediate 1: Gain update only on zero crossing.
bits : 3 - 3 (1 bit)
access : read-write

SAR_VREF : ADC VREF Selection
bits : 9 - 9 (1 bit)
access : read-write

EN_PGA : PGA enable control 0: Disable PGA 1: Enable PGA
bits : 10 - 10 (1 bit)
access : read-write

PD_IBEN : Analog bias power control 0: Power on analog bias generation 1: Power down analog bias generation
bits : 11 - 11 (1 bit)
access : read-write

IBGEN_TRIM : Set to 0
bits : 12 - 13 (2 bit)
access : read-write

MICB_EN : MICBIAS enable 0: Disable MIC_BIAS 1: Enable MIC_BIAS
bits : 16 - 16 (1 bit)
access : read-write

MICB_VSEL : Select MIC BIAS level.
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PGA_SEL : PGA Gain Selection. Range -18dB to +45dB, 1dB per step.
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MICP2PGA : MICP input enable 0 : disable(open) 1 : enable( short)
bits : 30 - 30 (1 bit)
access : read-write

MICN2PGA : MICN input enable 0 : disable(open) 1 : enable( short)
bits : 31 - 31 (1 bit)
access : read-write

PULLDWN : 0: Disable pull down VMID. 1: Enable pull down VMID reference to 0V.
bits : 0 - 0 (1 bit)
access : read-write

PDLOWRES : 0: Enable low resistance VMID reference. 1: Disconnect low resistance VMID reference.
bits : 1 - 1 (1 bit)
access : read-write

PDHIRES : 0: Enable high resistance VMID reference. 1: Disconnect high resistance VMID reference.
bits : 2 - 2 (1 bit)
access : read-write

SHCLK_N : Specify the high level of ADC start signal. Note: Suggested and default value is 0.
bits : 0 - 5 (6 bit)
access : read-write

CONV_N : Specify ADC conversion clock number CONV_N has to be equal to or great than 11. To update this field, programmer can only revise bit [14:8] and keep other bits the same as before. Note: CONV_N valid range is from 11~127
bits : 8 - 14 (7 bit)
access : read-write