Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
System Power Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL32K_WEAK : XTL32K weak mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal mode
#1 : 1
Weak mode
End of enumeration elements list.
XTL32K_EN : External 32.768KHz Crystal Control
After reset, this bit is 0 .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
32.768KHz Crystal is disabled
#1 : 1
32.768KHz Crystal is enabled
End of enumeration elements list.
OSC46M_EN : Internal 46MHz RC Oscillator Control
After reset, this bit is 1 .
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
46MHz oscillation is disabled
#1 : 1
46MHz oscillation is enabled
End of enumeration elements list.
XTL32K_FILTER : Filter the XTL32K output clock
Note: High level of XTL32K must keep 112 HCLK for recognition valid, when this bit is enabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable, XTL32K output clock without filter
#1 : 1
Enable, XTL32K output clock will be filtered to avoid glitch occurs
End of enumeration elements list.
WU_DLY : Enable the Wake Up Delay Time Selection
When the chip wakes up from power down, the clock control will delay some times as selection to wait LDO33 stable.
1: Delay 200us for LDO33 stable.
0: Delay 60us for LDO33 stable.
bits : 4 - 4 (1 bit)
access : read-write
WINT_EN : Enable Interrupt When Wake Up From Power Down Mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable. The interrupt will occur when MCU wakes up from power down mode
End of enumeration elements list.
WINT_STS : Chip Power Down Wake Up Status Flag
Set by power down wake up , it indicates that resume from power down mode.
The flag is set if the GPIO, WDT or RTC wakeup.
Note: Write 1 to clear the bit.
bits : 6 - 6 (1 bit)
access : read-write
PWR_DOWN : System Power Down Active Or Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operates at normal mode
#1 : 1
Chip is standing by power-down entry condition
End of enumeration elements list.
PD_WAIT_CPU : This Bit Controls the Power Down Entry Condition
Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit.
The following is a brief description of PD_WAIT_CPU bit.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip is at normal mode. Note that PWR_DOWN cannot be set to 1 when PD_WAIT_CPU value remains at 0, otherwise the chip may not wake up normally
#1 : 1
Chip waits to enter power-down mode
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Select
Note:
1. When power on, 23MHz RC is selected as HCLK clock source.
2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from XTL_32K
#010 : 2
clock source from PLL_23M
#100 : 4
clock source from PLL_23M
#111 : 7
clock source from RC_23M
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)
These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK/2048,
#01 : 1
Clock source from XTL_32K,
#10 : 2
Clock source from PLL_FOUT,
#11 : 3
Clock source from RC_23M
End of enumeration elements list.
ADCSEL : ADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from PLL_FOUT,
#01 : 1
Clock source from HCLK,.
Clock source from RC_46M
End of enumeration elements list.
SPI0SEL : SPI0 Clock Source Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK
#01 : 1
Clock source from PLL_FOUT.
Clock source from RC_46M
End of enumeration elements list.
TMR0SEL : Timer0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from XTL_32K.
Clock source from RC_46M
#010 : 2
Equivalent with 000
#011 : 3
Clock source from external trigger
End of enumeration elements list.
TMR1SEL : Timer1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from XTL_32K.
Clock source from RC_46M
#010 : 2
Equivalent with 000
#011 : 3
Clock source from external trigger
End of enumeration elements list.
TMR2SEL : Timer2 Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from XTL_32K.
Clock source from RC_46M
#010 : 2
Equivalent with 000
#011 : 3
Equivalent with 000
End of enumeration elements list.
TMRFSEL : TimerF Clock Source Select
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external XTL_32K/32,
#001 : 1
Clock source from external XTL_32K/(4x32),
#110 : 6
Clock source from RC_46M/32768,
#111 : 7
Clock source from RC_46M/(4x32768),
End of enumeration elements list.
PWMSEL : PWM Timer Clock Source Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK
#01 : 1
Clock source from XTL_32K
#10 : 2
Equivalent with 00
#11 : 3
Clock source from RC_46M
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
ADCDIV : ADC Clock Divide Number From ADC Clock Source
The ADC engine clock must meet the constraint: ADCLK ( HCKL/2.
bits : 16 - 23 (8 bit)
access : read-write
PLL Control Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHB Device Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPCKEN : OTP ISP Controller Clock Enable Control.
The OTP ISP engine clock always is from 46MHz RC oscillator.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the OTP ISP engine clock
#1 : 1
Enable the OTP ISP engine clock
End of enumeration elements list.
APUCKEN : APU Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
To disable the APU engine clock
#1 : 1
To enable the APU engine clock
End of enumeration elements list.
APB Device Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Clock Enable Control
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
The default bit value is set according to the Flash Controller User Configuration Register CONFIG[31].
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
RTC_EN : Real-Time-Clock APB Interface Clock Control
This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
TMRF_EN : TimerF Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
PWM_EN : PWM Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
ADC_EN : Audio Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable
#1 : 1
Enable
End of enumeration elements list.
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