Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go And Busy Status
NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI core has no effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit starts the transfer. This bit remains 1 during the transfer and is automatically cleared after the transfer is finished
End of enumeration elements list.
RX_NEG : Receive On Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input on SPI_MISO0 is latched on the rising edge of SPI_SCLK0
#1 : 1
The input on SPI_MISO0 is latched on the falling edge of SPI_SCLK0
End of enumeration elements list.
TX_NEG : Transmit On Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output on SPI_MOSI0 is changed on the rising edge of SPI_SCLK0
#1 : 1
The output on SPI_MOSI0 is changed on the falling edge of SPI_SCLK0
End of enumeration elements list.
DWIDTH : Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Transmit/Receive Numbers
This field specifies how many transmit/receive numbers should be executed in one transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive will be executed in one transfer
#01 : 1
Two successive transmit/receive will be executed in one transfer.
Reserved
End of enumeration elements list.
LSB : Send LSB First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first (which bit in SPI0_TXn/SPI0_RXn is MSB is dependent on DWIDTH)
#1 : 1
The LSB (SPI0_TXn[0]) is sent first to SPI0_MOSI0, and the first bit received from SPI0_MISO0 will be put in the LSB (SPI0_RXn[0])
End of enumeration elements list.
CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI_SCLK0 idle low
#1 : 1
SPI_SCLK0 idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Mode Only)
(SUSPITV+2)* SPI0_CLK clock cycles
Note: SUSPITV cannot be 0 .
bits : 12 - 15 (4 bit)
access : read-write
UNIT_INTSTS : Unit Transfer Interrupt Status
Note: This bit is read only, but can be cleared by writing 1 to this bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
UNIT_INTEN : Unit Transfer Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Unit Transfer Interrupt
#1 : 1
Enable SPI Unit Transfer Interrupt to CPU
End of enumeration elements list.
SLAVE : Master/Slave Mode Select
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : BYTE ENDIAN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the BYTE ENDIAN
#1 : 1
Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in DWIDTH are supported
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
bits : 0 - 31 (32 bit)
access : read-only
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
Note: The SPI0_RXn and SPI0_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI0_TXn register between the two transfers.
bits : 0 - 31 (32 bit)
access : write-only
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0 Receive Timing Control Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI0_FTIM : Fine Timing Control For SPI0 Data Receiving
The delay timing selected by SPI0_CTIM can be further tuned finely by SPI0_FTIM.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Receiving data clock of SPI0 has extra 7.5nS delay
#01 : 1
Receiving data clock of SPI0 has extra 5.0nS delay,
#10 : 2
Receiving data clock of SPI0 has extra 2.5nS delay,
#11 : 3
Receiving data clock of SPI0 has no extra delay
End of enumeration elements list.
SPI0_CTIM : Coarse Timing Control For SPI0 Data Receiving
Setting these bits can adjust receiving clock for latching serial-in data correctly in high speed transmission mode.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Receiving data clock of SPI0 is same as the SPI_SCLK0
#01 : 1
Receiving data clock of SPI0 is delayed 2 half SPI_SCLK0 clock cycle,
#10 : 2
Receiving data clock of SPI0 is delayed 3 half SPI_SCLK0 clock cycle,
#11 : 3
Receiving data clock of SPI0 is delayed 1 half SPI_SCLK0 clock cycle ,
End of enumeration elements list.
Clock Divider Register (Master Only)
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register (Master Mode Only)
SPI0 clock pin SPI_SCLK0 output clock frequency is SPI0_CIN/(DIVIDER+1).DIVIDER can be from 0 to 65535. But due to I/O transaction speed limitation, the maximum clock of SPI_SCLK0 is 23 MHz. So the DIVIDER value cannot be set to 0 when RC_46M is selected as the SPI clock source.
bits : 0 - 15 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Select Pin Control
If AUTOSS bit is 0,
SPI0_SSB00 and SPI0_SSB01 output are determined by SS[0] and SS[1] respectively.
Note 1: This interface can only drive one device/slave at a given time. Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
Note 2: SPIn_SSB10 is also defined as device/slave select input signal in slave mode. And that the slave select input signal must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active trigger again or reset the SPI core by software.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
Any bit location of this field forces the pin to inactive state.
Any bit location of this field will select appropriate SPI0_SSB00/SPI0_SSB01 pin to be driven to inactive state
1 : 1
Any bit location of this field forces the proper SPIn_SSBx0/SPIn_SSBx1 pin to an active state
Any bit location of this field will select appropriate SPIn_SSB00/SPIn_SSB01 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time. The active state of SPI0_SSB00/SPI0_SSB01 is specified in SS_LVL bit (SPI_SSCTL[2])
End of enumeration elements list.
SS_LVL : Slave Select Active Level
It defines the active level of device/slave select signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI_SSB00/SPI_SSB01 slave select signal is active Low
#1 : 1
The SPI_SSB00/SPI_SSB01 slave select signal is active High
End of enumeration elements list.
AUTOSS : Automatic Slave Select (Master Mode Only)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select signal (SPI_SSB00/SPI_SSB01) is asserted and de-asserted by setting and clearing related bit SS
#1 : 1
Slave select signal (SPI_SSB00/SPI_SSB01) is generated automatically. It means that slave select signal, which is set in bits SS, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger (Slave Mode Only)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger. This is the default value
#1 : 1
The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Flag (Slave Mode Only)
When the SS_LTRIG bit is set in slave mode, this bit can be read to indicate the received bit number meets the requirement or not.
Note 1: This bit is READ only.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
One of the received number and the received bit length doesn't meet the requirement in one transfer
#1 : 1
The received number and received bits meet the requirement which is defined in TX_NUM and DWIDTH among one transfer
End of enumeration elements list.
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