Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x18 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x30 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :
Product Identifier Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Product Identifier
Chip identifier (part number) for N572F064 series.
bits : 0 - 31 (32 bit)
access : read-only
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Protected Register Lock/Unlock Index (Read Only)
SPI0_RCLK - address 0x4003_0030
FMC_ISPCTL - address 0x5000_C000 (Flash ISP Control register)
WDT_CTL - address 0x4000_4000
FATCON - address 0x5000_C018
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Protected registers are locked. Any write to the target register is ignored
#1 : 1
Protected registers are unlocked
End of enumeration elements list.
SYS_REGLCTL : Register Lock Control Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
bits : 0 - 7 (8 bit)
access : write-only
Brown-Out Detector Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOD_EN : Brown-Out Detector Enable (Initiated and Protected Bit)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-Out Detector function is disabled
#1 : 1
Brown-Out Detector function is enabled,
End of enumeration elements list.
BOD_VL : Brown-Out Detector Threshold Voltage Selection (Initiate and Protected Bit)
The default value is set by flash controller user configuration register CONFIG[21].
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Threshold voltage is 2.7V
#1 : 1
Threshold voltage is 3.0V
End of enumeration elements list.
BOD_OUT : The Status For Brown-Out Detector Output It's a read only bit.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The detected voltage is lower than BOD_VL setting. If the BOD_EN is 0 , this bit always responses 0
#1 : 1
The detected voltage is higher than BOD_VL setting
End of enumeration elements list.
LVR_EN : Low Voltage Reset (LVR) Enable (Protected Bit)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled in default.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable LVR function
#1 : 1
Enable LVR function - After enable the bit, the LVR function will active with 100uS delay for LVR output stable
End of enumeration elements list.
Power-On-Reset Controller Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-On Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, ICE reset command and the software-chip reset function.
bits : 0 - 15 (16 bit)
access : read-write
GPIO PA Multiple Alternate Functions and Input Type Control Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-0 is selected to the pin PA.0
#1 : 1
SPI0 2nd chip select output
End of enumeration elements list.
PA1MFP :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-1 is selected to the pin PA.1
#1 : 1
SPI0 1st chip select output
End of enumeration elements list.
PA2MFP :
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-2 is selected to the pin PA.2
#1 : 1
SPI0 clock output
End of enumeration elements list.
PA3MFP :
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-3 is selected to the pin PA.3
#1 : 1
SPI0 data input
End of enumeration elements list.
PA4MFP :
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-4 is selected to the pin PA.4
#1 : 1
SPI0 data output
End of enumeration elements list.
PA5MFP :
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-5 is selected to the pin PA.5
#1 : 1
Timer0 counter external input
End of enumeration elements list.
PA6MFP :
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-6 is selected to the pin PA.6
#1 : 1
External interrupt input
End of enumeration elements list.
PA7MFP :
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-7 is selected to the pin PA.7
#1 : 1
ADC input external trigger input
End of enumeration elements list.
PA8MFP :
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-8 is selected to the pin PA.8
#1 : 1
ADC input channel 0
End of enumeration elements list.
PA9MFP :
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-9 is selected to the pin PA.9
#1 : 1
ADC input channel 1
End of enumeration elements list.
PA10MFP :
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-10 is selected to the pin PA.10
#1 : 1
ADC input channel 2
End of enumeration elements list.
PA11MFP :
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-11 is selected to the pin PA.11
#1 : 1
ADC input channel 3
End of enumeration elements list.
PA12MFP :
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-12 is selected to the pin PA.12
#1 : 1
ADC input channel 4
End of enumeration elements list.
PA13MFP :
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-13 is selected to the pin PA.13
#1 : 1
ADC input channel 5
End of enumeration elements list.
PA14MFP :
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-14 is selected to the pin PA.14
#1 : 1
ADC input channel 6
End of enumeration elements list.
PA15MFP :
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOA-15 is selected to the pin PA.15
#1 : 1
ADC input channel 7
End of enumeration elements list.
PAnTYPEn :
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
PA.n I/O cell input Schmitt Trigger function is disabled
1 : 1
PA.n I/O cell input Schmitt Trigger function is enabled
End of enumeration elements list.
GPIO PB Multiple Alternate Functions and Input Type Control Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-0 is selected to the pin PB.0
#1 : 1
SPI1 2nd chip select output
End of enumeration elements list.
PB1MFP :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-1 is selected to the pin PB.1
#1 : 1
SPI1 1st chip select output or slave select input
End of enumeration elements list.
PB2MFP :
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-2 is selected to the pin PB.2
#1 : 1
SPI1 clock output/input
End of enumeration elements list.
PB3MFP :
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-3 is selected to the pin PB.3
#1 : 1
SPI1 data input/output
End of enumeration elements list.
PB4MFP :
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-4 is selected to the pin PB.4
#1 : 1
SPI1 data output/input
End of enumeration elements list.
PB8MFP :
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-8 is selected to the pin PB.8
#1 : 1
PWM output pin 0
End of enumeration elements list.
PB9MFP :
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-9 is selected to the pin PB.9
#1 : 1
PWM output pin 1
End of enumeration elements list.
PB10MFP :
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-10 is selected to the pin PB.10
#1 : 1
PWM output pin 2
End of enumeration elements list.
PB11MFP :
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-11 is selected to the pin PB.11
#1 : 1
PWM output pin 3
End of enumeration elements list.
PB12MFP :
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-12 is selected to the pin PB.12
#1 : 1
PWM timer capture input
End of enumeration elements list.
PB13MFP :
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-13 is selected to the pin PB.13
#1 : 1
IR carrier output
End of enumeration elements list.
PB14MFP :
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-14 is selected to the pin PB.14
#1 : 1
Timer1 counter external input
End of enumeration elements list.
PB15MFP :
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIOB-15 is selected to the pin PB.15
#1 : 1
Timer2 counter external input
End of enumeration elements list.
PBnTYPEn :
bits : 16 - 31 (16 bit)
access : read-write
Enumeration:
0 : 0
PB.n I/O cell input Schmitt Trigger function is disabled
1 : 1
PB.n I/O cell input Schmitt Trigger function is enabled
End of enumeration elements list.
System Reset Source Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR
#1 : 1
Power-on Reset (POR) Controller had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : nRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : Reset Source From WDG
The WDTRF flag is set if pervious reset source originates from the Watch-Dog module.
Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Watch-Dog
#1 : 1
The Watch-Dog module issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
LVR controller had issued the reset signal to reset the system
End of enumeration elements list.
MCURF : MCU Reset Flag
The MCURF flag is set by the reset signal from the MCU Cortex_M0 module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from MCU
#1 : 1
The MCU Cortex_M0 had issued the reset signal to reset the system
End of enumeration elements list.
PMURSTF : Reset Source From PMU
The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from PMU
#1 : 1
The PMU has issued the reset signal to reset the system
End of enumeration elements list.
IP Reset Control Resister0
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : CHIP One Shot Reset
Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles.
The CHIPRST is almost the same as the POR reset, all the chip modules are reset but the chip settings from flash are not reloaded.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CHIP
End of enumeration elements list.
CPURST : CPU Kernel One Shot Reset
Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal
#1 : 1
Reset CPU
End of enumeration elements list.
CPUWS : CPU Wait-State Control For Flash Memory Access
Note: that CPUWS cannot be set as 1 when CPU runs the program to do Flash ISP operation.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 HCLK clock wait-state
#1 : 1
zero wait-state
End of enumeration elements list.
RAMWS : Wait State Control For CPU Access RAM
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
1 HCLK clock wait-state
#1 : 1
zero wait-state
End of enumeration elements list.
IP Reset Control Resister1
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
IP reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
IP reset
End of enumeration elements list.
APURST : APU Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
IP reset
End of enumeration elements list.
TMRFRST : TimerF Controller Reset
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
IP reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
PWMRST : PWM Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
USBDRST : USB Device Controller Reset
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
IP reset
End of enumeration elements list.
ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal Operation
#1 : 1
IP reset
End of enumeration elements list.
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