CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKDIV (CLKDIV)

CLK_PLLCON (PLLCON)

CLK_AHBCLK (AHBCLK)

CLK_APBCLK (APBCLK)

XTL12M_EN : External 12MHz (or 6MHz) Crystal Oscillator Control This bit is set by the combination logic of flash controller user configuration register CONFIG[26:24] after power on.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

XTL32K_EN : External 32.768KHz Crystal Control After reset, this bit is 0 .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OSC24M_EN : Internal 24MHz Oscillator Control After reset, this bit is 1 .
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VOUTX_PD : Driving Out 3.0V (Through VOUTX Pad) LDO Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WU_DLY : Enable The Wake Up Delay Counter When the chip wakes up from idle mode, the clock control will delay some clock cycles to wait the 12MHz (or 6MHz) crystal or the internal 24MHz oscillator clock stable.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WINT_EN : Enable Interrupt When Wake Up From Power Down Mode
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WINT_STS : Chip Power Down Wake Up Status Flag Set by power down wake up , it indicates that resume from power down mode. The flag is set if the GPIO, USB, WDT or RTC wakeup. Note: Write 1 to clear the bit.
bits : 6 - 6 (1 bit)
access : read-write

PWR_DOWN : System Power Down Active Or Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_WAIT_CPU : This Bit Controls The Power Down Entry Condition Please refer to PWR_DOWN bit for the usage of PD_WAIT_CPU bit. The following is a brief description of PD_WAIT_CPU bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKSEL : HCLK clock source select. Note: 1. Before clock switch, the related clock sources (pre-select and new-select) must be turned on. 2. The 3-bit default value is reloaded with the value of CFOSC (CONFIG[26:24]) in user configuration register in Flash controller by any reset. Therefore the default value is either 001b or 111b. Besides, before chip enters power down mode, HCLKSEL only can be either 001b or 111b.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect) These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCSEL : ADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : Timer0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1SEL : Timer1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2SEL : Timer2 Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMRFSEL : TimerF Clock Source Select
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWMSEL : PWM Timer Clock Source Select
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write

ADCDIV : ADC Clock Divide Number From ADC Clock Source The ADC clock must meet the constraint: ADCLK ( HCKL/2
bits : 16 - 23 (8 bit)
access : read-write

ISPCKEN : Flash ISP Engine Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_EN : Watchdog Clock Enable Control This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100. The default bit value is set according to the Flash Controller User Configuration Register CONFIG[31].
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-Time-Clock APB Interface Clock Control This bit is used to control the RTC APB clock only. The RTC engine clock source is from the 32.768KHz crystal.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMRF_EN : TimerF Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable Control
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM_EN : PWM Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBD_EN : USB FS Device Controller Clock Enable Control
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Audio Analog-Digital-Converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APU_EN : APU Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.