PA_MODE

PA_PIN

PA_INTTYPE

PA_INTEN

PA_INTSRC

PA_DINOFF

PB_MODE

PB_DINOFF

PB_DOUT

PB_DATMSK

PB_PIN

PB_INTTYPE

PB_INTEN

PB_INTSRC

PA_DOUT

PA_DATMSK

MODE0 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE1 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE2 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE3 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE4 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE5 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE6 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE7 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE8 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE9 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE10 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE11 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE12 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE13 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE14 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE15 : Port [A/B] Pin[N] I/O Mode Control Determine each I/O type of GPIO Px pins
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN : Port [A/B] Pin[N] Pin Values Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1, it indicates the corresponding pin status is high else the pin status is low.
bits : 0 - 15 (16 bit)
access : read-only

TYPE : Port [A/B] Pin[N] Edge Or Level Detection Interrupt Trigger Type Control TYPE[n] is used to control whether the interrupt mode is level triggered or edge triggered. If the interrupt mode is level triggered, the input source is sampled by one HCLK clock to generate the interrupt Note: If level triggered interrupt is selected, then only one level can be selected in the Px_INTEN register. If both levels are set, the setting is ignored and no interrupt will occur
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN0 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN1 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN2 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN3 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN4 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN5 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN6 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN7 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN8 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN9 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN10 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN11 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN12 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN13 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN14 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLIEN15 : Port [A/B] Interrupt Enable By Input Falling Edge Or Input Level Low FLIEN[n] is used to enable the falling/low-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the FLIEN[n] (Px_INTEN[n]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at low level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from high to low.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN0 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN1 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN2 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN3 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN4 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN5 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN6 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN7 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN8 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN9 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN10 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN11 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN12 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN13 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN14 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RHIEN15 : Port [A/B] Interrupt Enable By Input Rising Edge Or Input Level High RHIEN[n] is used to enable the rising/high-level interrupt for each of the corresponding input Px.n pin. To set 1 also enables the pin wake-up function. When setting the RHIEN[n] (Px_INTEN[n+16]) bit to 1 : If the interrupt is configured as level trigger mode (TYPE[n] is set to 1), one interrupt will occur while the input Px.n state is at high level. If the interrupt is configured as edge trigger mode (TYPE[n] is set to 0), one interrupt will occur while he input Px.n state changes from low to high.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTSRC : Port [A/B] Interrupt Source Flag Read operation:
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF0 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF1 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF2 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF3 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF4 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF5 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF6 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF7 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF8 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF9 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF10 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF11 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF12 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF13 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF14 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DINOFF15 : Port [A/B] Pin[N] Digital Input Path Disable Control
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DOUT : Port [A/B] Pin[N] Output Value Each of these bits controls the status of a GPIO pin when the GPIO pin is configured as output, open-drain or quasi-bidirectional mode.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATMSK : Port [A/B] Pin[N] Data Output Write Mask These bits are used to protect the corresponding register of Px_DOUT[n]. When set the DATMSK[n] to 1 , the corresponding Px_DOUT[n] bit is writing protected.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.