\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
address_offset : 0x10 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go And Busy Status
NOTE: All registers should be set readily before writing 1 to the GO_BUSY bit. When a transfer is in progress, writing to any register of the SPI core has no effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit starts the transfer. This bit remains 1 during the transfer and is automatically cleared after the transfer is finished
End of enumeration elements list.
RX_NEG : Receive On Negative Edge
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input on SPI_MISOn is latched on the rising edge of SPI_SCLKn
#1 : 1
The input on SPI_MISOn is latched on the falling edge of SPI_SCLKn
End of enumeration elements list.
TX_NEG : Transmit On Negative Edge
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output on SPI_MOSIn is changed on the rising edge of SPI_SCLKn
#1 : 1
The output on SPI_MOSIn is changed on the falling edge of SPI_SCLKn
End of enumeration elements list.
DWIDTH : Transmit Bit Length
This field specifies how many bits are transmitted in one transmit/receive. Up to 32 bits can be transmitted.
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Transmit/Receive Numbers
This field specifies how many transmit/receive numbers should be executed in one transfer.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Only one transmit/receive will be executed in one transfer
#01 : 1
Two successive transmit/receive will be executed in one transfer.
Reserved
End of enumeration elements list.
LSB : Send LSB First
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB is transmitted/received first (which bit in SPI_TXn/SPI_RXn is MSB is dependent on DWIDTH)
#1 : 1
The LSB (SPI_TXn[0]) is sent first to SPI_MOSIn, and the first bit received from SPI_MISOn will be put in the LSB (SPI_RXn[0])
End of enumeration elements list.
CLKP : Clock Polarity
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI_SCLKn idle low
#1 : 1
SPI_SCLKn idle high
End of enumeration elements list.
SUSPITV : Suspend Interval (Master Mode Only)
(SUSPITV+2)* SPI_SCLKn clock cycles
Note: SUSPITV cannot be 0 for SPI0.
bits : 12 - 15 (4 bit)
access : read-write
UNIT_INTSTS : Unit Transfer Interrupt Status
Note: This bit is read only, but can be cleared by writing 1 to this bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
UNIT_INTEN : Unit Transfer Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable SPI Unit Transfer Interrupt
#1 : 1
Enable SPI Unit Transfer Interrupt to CPU
End of enumeration elements list.
REORDER : BYTE ENDIAN
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the BYTE ENDIAN
#1 : 1
Enable the BYTE ENDIAN. Only the 16, 24, and 32 bits which are defined in DWIDTH are supported
End of enumeration elements list.
Data Receive Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register
Note: The Data Receive Registers are read only registers. A Write to these registers will actually modify the Data Transmit Registers because those registers share the same flip-flops.
bits : 0 - 31 (32 bit)
access : read-only
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Data Transmit Register 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register
Note: The SPI_RXn and SPI_TXn registers share the same flip-flops, which mean that what is received in one transfer will be transmitted in the next transfer if there is not any write to the SPI_TXn register between the two transfers.
bits : 0 - 31 (32 bit)
access : write-only
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider Register
The value in this field is the frequency divider of the system clock, PCLK, to generate the serial clock on the output (SPICLK).The desired frequency is obtained according to the following equation:
/
NOTE: Suggest DIVIDER should be at least 1 in master mode.
bits : 0 - 15 (16 bit)
access : read-write
Slave Select Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SS : Slave Select Pin Control (Master Mode Only)
If AUTOSS bit is 0,
SPIn_SSBx0 and SPIn_SSBx1 output are determined by SS[0] and SS[1] respectively.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : 0
Any bit location of this field forces the pin to inactive state.
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be driven to inactive state
1 : 1
Any bit location of this field forces the proper SPIn_SSBx0/SPIn_SSBx1 pin to an active state
Any bit location of this field will select appropriate SPIn_SSBx0/SPIn_SSBx1 pin to be automatically driven to active state for the duration of the transmit/receive, and to be driven to inactive state for the rest of the time. The active state of SPIn_SSBx0/SPIn_SSBx1 is specified in SS_LVL bit (SPI_SSCTL[2])
End of enumeration elements list.
SS_LVL : Slave Select Active Level
It defines the active level of device/slave select signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPI_SSBx0/SPI_SSBx1 slave select signal is active Low
#1 : 1
The SPI_SSBx0/SPI_SSBx1 slave select signal is active High
End of enumeration elements list.
AUTOSS : Automatic Slave Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select signal (SPI_SSBx0/SPI_SSBx1) is asserted and de-asserted by setting and clearing related bit SS
#1 : 1
Slave select signal (SPI_SSBx0/SPI_SSBx1) is generated automatically. It means that slave select signal, which is set in bits SS, is asserted by the SPI controller when transmit/receive is started by setting GO_BUSY, and is de-asserted after the transfer is finished
End of enumeration elements list.
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