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APU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :

address_offset : 0xC Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :

Registers

APU_CTL (CTL)

APU_CH0DAT0 (CH0DAT0)

CH0DAT1

CH0DAT2

CH0DAT3

CH0DAT4

CH0DAT5

CH0DAT6

CH0DAT7

APU_VM (VM)

APU_CH1DAT0 (CH1DAT0)


APU_CTL (CTL)

APU Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APU_CTL APU_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSHD APUIS APUIE PAMPE DACE BPPAM DACGN

TSHD : APU Interrupt Threshold
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Buffer 0 is read out by APU

#001 : 1

Buffer 1 is read out by APU

#010 : 2

Buffer 2 is read out by APU

#011 : 3

Buffer 3 is read out by APU

#100 : 4

Buffer 4 is read out by APU

#101 : 5

Buffer 5 is read out by APU

#110 : 6

Buffer 6 is read out by APU

#111 : 7

Buffer 7 is read out by APU

End of enumeration elements list.

APUIS : APU Interrupt Status This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

APU threshold interrupt does not occur

#1 : 1

APU threshold interrupt occur

End of enumeration elements list.

APUIE : APU Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable the APU threshold interrupt

#1 : 1

Enable the APU threshold interrupt

End of enumeration elements list.

PAMPE : Power Amplifier Enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable PA function

#1 : 1

Enable PA function

End of enumeration elements list.

DACE : DAC Enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable DAC function

#1 : 1

Enable DAC function

End of enumeration elements list.

BPPAM : Bypass Power Amplifier, DAC Output To Pin Note: User must set BPPAM to 0 to use SPK+ and SPK- as the power amplifier outputs.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPK+ and SPK- are power amplifier outputs

#1 : 1

No output at SPK-. This setting is for testing only and prohibited for normal operation

End of enumeration elements list.

DACGN : DAC Output Current Control This bit is effective only when BPPAM is 1 .
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

3mA

#1 : 1

5mA

End of enumeration elements list.


APU_CH0DAT0 (CH0DAT0)

APU Channel 0 Data Buffer Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APU_CH0DAT0 APU_CH0DAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM

PCM : PCM Data Of Channel 0 This field contains 13 bits PCM data that is one of the mixer input. The data format of PCM is 2'complement.
bits : 0 - 12 (13 bit)
access : read-write


CH0DAT1


address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT1 CH0DAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT2


address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT2 CH0DAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT3


address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT3 CH0DAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT4


address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT4 CH0DAT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT5


address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT5 CH0DAT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT6


address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT6 CH0DAT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CH0DAT7


address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0DAT7 CH0DAT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

APU_VM (VM)

APU Volume Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APU_VM APU_VM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOLUM

VOLUM : APU Volume Adjustment
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

0 dB

#001 : 1

-3 dB

#010 : 2

-6 dB

#011 : 3

-9 dB

#100 : 4

-12 dB

#101 : 5

-15 dB

#110 : 6

-18 dB

#111 : 7

Reserved

End of enumeration elements list.


APU_CH1DAT0 (CH1DAT0)

APU Channel 1 Data Buffer Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APU_CH1DAT0 APU_CH1DAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM1

PCM1 : PCM Data Of Channel 1 This field contains 13 bits PCM data that is one of the mixer input. The data format of PCM is 2'complement.
bits : 0 - 12 (13 bit)
access : read-write



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