ADC_DAT0 (DAT0)

DAT4

DAT5

DAT6

DAT7

ADC_CTL (CTL)

ADC_CHSEQ (CHSEQ)

ADC_CMP0 (CMP0)

CMP1

ADC_STATUS (STATUS)

ADC_CAL (CAL)

ADC_PGCTL (PGCTL)

DAT1

DAT2

DAT3

RESULT : A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADCFM bit.
bits : 0 - 11 (12 bit)
access : read-only

EXTS : Extension Bits Of RESULT for Different Data Format If ADCFM is 0 , EXTS all are read as 0 . If ADCFM is 1 , EXTS all are read as bit RESULT[11].
bits : 12 - 15 (4 bit)
access : read-only

OV : Over Run Flag If converted data in RESULT[11:0] have not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after ADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VALID : Valid Flag This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

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ADCEN : A/D Converter Enable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCIE : A/D Interrupt Enable A/D conversion end interrupt request is generated if ADCIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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OPMODE : A/D Converter Operation Mode When changing the operation mode, software should disable SWTRG bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

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HWTRGCOND : Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

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HWTRGEN : Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D Conversion Start Note: SWTRG bit can be set to 1 from three sources: software write and external pin STADC. SWTRG is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCFM : Data Format Of ADC Conversion Result
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

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CHSEQ0 : Select Channel N As The 1st Conversion In Scan Sequence
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

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CHSEQ1 : Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 4 - 7 (4 bit)
access : read-write

CHSEQ2 : Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 8 - 11 (4 bit)
access : read-write

CHSEQ3 : Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 12 - 15 (4 bit)
access : read-write

CHSEQ4 : Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 16 - 19 (4 bit)
access : read-write

CHSEQ5 : Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 20 - 23 (4 bit)
access : read-write

CHSEQ6 : Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 24 - 27 (4 bit)
access : read-write

CHSEQ7 : Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 28 - 31 (4 bit)
access : read-write

ADCMPEN : Compare Enable Set this bit to 1 to enable the comparison CMPDAT[11:0] with specified channel conversion result when converted data is loaded into ADC_DAT register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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ADCMPIE : Compare Interrupt Enable When converted data in RESULT is less (or greater) than the compare data CMPDAT[11:0], ADCMPF bit is asserted. If ADCMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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CMPCH : Compare Channel Selection
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

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CMPMCNT : Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMCNT+1) hardware will set the ADCMPF bit.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Compare Data The 12 bits data are used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADCFM bit.
bits : 16 - 27 (12 bit)
access : read-write

ADIF : A/D Conversion End Flag A status flag that indicates the end of A/D conversion. ADIF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP0, then this bit is set to 1. And it is cleared by write 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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ADCMPF1 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADC_CMP1, then this bit is set to 1. And it is cleared by write 1.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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BUSY : BUSY/IDLE This bit is mirror of SWTRG bit in ADC_CTL. It is read only.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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CHANNEL : Current Conversion Channel It is read only.
bits : 4 - 6 (3 bit)
access : read-write

VALID : Data Valid Flag It is a mirror of VALID bit in ADC_DATn.
bits : 8 - 15 (8 bit)
access : read-write

OV : Over Run Flag It is a mirror to OV bit in ADC_DATn.
bits : 16 - 23 (8 bit)
access : read-write

CALEN : Self-Calibration Enable Software can set this bit to 1 enables A/D converter to do self-calibration function. It needs 127 ADC clocks to complete calibration. This bit must be kept at 1 after CALDONE asserted. Clearing this bit will disable self-calibration function.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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CALDONE : Calibration is Done (read only) When 0 is written to CALEN bit, CALDONE bit is cleared by hardware immediately and be set to 1 after 96 ADC clocks. It is a read only bit.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

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OPMUTE : Mute Control of First Stage Pre-Amp for Offset Bias Calibration When this bit is set as 1 , two input end of first stage pre-amp will be shorted, and feedback resistor of this stage will be shorted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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PAG_II : Gain Setting Bits for the Second Stage Of Pre-Amp
bits : 1 - 5 (5 bit)
access : read-write

Enumeration:

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OS : Configuration for Pre-Amp OP Offset Bias Compensation Voltage There are 32 levels and 2mV per level @ 5V condition.
bits : 6 - 10 (5 bit)
access : read-write

PAG_I : Gain Setting Bits for the First Stage Of Pre-Amp
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.