\n

FMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :

address_offset : 0x18 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection :

Registers

FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_FAT (FAT)

FMC_ISPADDR (ISPADDR)

FMC_ISPDAT (ISPDAT)

FMC_ISPCMD (ISPCMD)


FMC_ISPCTL (ISPCTL)

ISP Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_ISPCTL FMC_ISPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPEN EWEN CFGUEN ISPFF PT ET

ISPEN : ISP Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable ISP function

#1 : 1

Enable ISP function

End of enumeration elements list.

EWEN : Enable Erase/Write Of ISP Function
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable erase/write

#1 : 1

Enable erase/write

End of enumeration elements list.

CFGUEN : CONFIG Update Enable When enabled, ISP functions can access the CONFIG address space and modify device configuration area.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable

#1 : 1

Enable

End of enumeration elements list.

ISPFF : ISP Fail Flag This bit is set by hardware when a triggered ISP meets any of the following conditions: MCU writes (or erase) to Flash when EWEN is 0 . Destination address is illegal, such as over an available range. Write 1 to clear.
bits : 6 - 6 (1 bit)
access : read-write

PT : Flash Program Time
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

40 (s (default)

#001 : 1

45 (s

#010 : 2

50 (s

#011 : 3

55 (s

#100 : 4

20 (s

#101 : 5

25 (s

#110 : 6

30 (s

#111 : 7

35 (s

End of enumeration elements list.

ET : Flash Page Erase Time
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

20 ms (default)

#001 : 1

25 ms

#010 : 2

30 ms

#011 : 3

35 ms

#100 : 4

3 ms

#101 : 5

5 ms

#110 : 6

10 ms

#111 : 7

15 ms

End of enumeration elements list.


FMC_ISPTRG (ISPTRG)

ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_ISPTRG FMC_ISPTRG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPGO

ISPGO : ISP Start Trigger Write 1 to start ISP operation. This bit will be cleared to 0 by hardware automatically when ISP operation is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

ISP operation is finished

#1 : 1

ISP is ongoing

End of enumeration elements list.


FMC_FAT (FAT)

Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_FAT FMC_FAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FMC_ISPADDR (ISPADDR)

ISP Address Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_ISPADDR FMC_ISPADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPADDR

ISPADDR : ISP Address Register This is the memory address register that a subsequent ISP command will access. ISP operation are carried out on 32-bit word only, consequently ISPADDR [1:0] must be 00b for correct ISP operation. N572F064 equips with an 16Kx32 bits embedded flash.
bits : 0 - 31 (32 bit)
access : read-write


FMC_ISPDAT (ISPDAT)

ISP Data Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_ISPDAT FMC_ISPDAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISPDAT

ISPDAT : ISP Data Register Write data to this register before an ISP program operation. Read data from this register after an ISP read operation
bits : 0 - 31 (32 bit)
access : read-write


FMC_ISPCMD (ISPCMD)

ISP Command Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FMC_ISPCMD FMC_ISPCMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : ISP Command Operation Mode : CMD -------------------- ------- Standby : 0x3X Read CID : 0x0B Read DID : 0x0C Flash Page Erase : 0x22 Flash Program : 0x21 Flash Read : 0x00
bits : 0 - 5 (6 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.