\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
address_offset : 0xC Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection :
APU Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSHD : APU Interrupt Threshold
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Buffer 0 is read out by APU
#001 : 1
Buffer 1 is read out by APU
#010 : 2
Buffer 2 is read out by APU
#011 : 3
Buffer 3 is read out by APU
#100 : 4
Buffer 4 is read out by APU
#101 : 5
Buffer 5 is read out by APU
#110 : 6
Buffer 6 is read out by APU
#111 : 7
Buffer 7 is read out by APU
End of enumeration elements list.
APUIS : APU Interrupt Status
This flag is set by hardware when APU threshold is met. Software can clear this bit by writing a zero to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
APU threshold interrupt does not occur
#1 : 1
APU threshold interrupt occur
End of enumeration elements list.
APUIE : APU Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the APU threshold interrupt
#1 : 1
Enable the APU threshold interrupt
End of enumeration elements list.
PAMPE : Power Amplifier Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable PA function
#1 : 1
Enable PA function
End of enumeration elements list.
DACE : DAC Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable DAC function
#1 : 1
Enable DAC function
End of enumeration elements list.
BPPAM : Bypass Power Amplifier, DAC Output To Pin
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPK+/DAC pin is one of power amplifier output,
#1 : 1
SPK+/DAC pin is current DAC output, no output on SPK-
End of enumeration elements list.
DACGN : DAC Output Current Control
This bit is effective only when BPPAM is 1 .
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
3mA
#1 : 1
5mA
End of enumeration elements list.
APU channel 0 Data Buffer Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCM : PCM Data Of Channel 0
This field contains 16-bit PCM data that will be sent to Mixer APU H/W.
User needs to take care of the effective bit of PCM because the H/W Mixer output is clipped to 13 bits automatically.
The data format of PCM is 2'complement.
bits : 0 - 15 (16 bit)
access : read-write
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APU Volume Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VOLUM : APU Volume Adjustment
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
0 dB
#001 : 1
-3 dB
#010 : 2
-6 dB
#011 : 3
-9 dB
#100 : 4
-12 dB
#101 : 5
-15 dB
#110 : 6
-18 dB
#111 : 7
Reserved
End of enumeration elements list.
APU channel 1 Data Buffer Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCM : PCM Data Of Channel 1
This field contains 16-bit PCM data that are one of the Mixer input.
User needs to take care of the effective bit of PCM because the H/W mixer output is clipped to 13 bits automatically.
The data format of PCM is 2'complement.
bits : 0 - 15 (16 bit)
access : read-write
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