ADC_DAT0 (DAT0)

DAT4

DAT5

DAT6

DAT7

ADC_CTL (CTL)

ADC_CHSEQ (CHSEQ)

ADC_CMP0 (CMP0)

CMP1

ADC_STATUS (STATUS)

ADC_PGCTL (PGCTL)

DAT1

ADC_MIBSCTL (MIBSCTL)

DAT2

DAT3

RESULT : A/D Conversion Result This field contains the 12-bit conversion result. Its data format is defined by ADFM bit.
bits : 0 - 11 (12 bit)
access : read-only

EXTS : Extension Bits Of RSLT For Different Data Format If ADFM is 0 , EXTS all are read as 0 . If ADFM is 1 , EXTS all are read as bit RSLT[11].
bits : 12 - 15 (4 bit)
access : read-only

OV : Over Run Flag 1: Data in RSLT are overwritten. 0: Data in RSLT are recent conversion result. If converted data in RSLT have not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADCDR register is read.
bits : 16 - 16 (1 bit)
access : read-only

VALID : Valid Flag 1: Data in RSLT are valid. 0: Data in RSLT are not valid. This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADCDR register is read.
bits : 17 - 17 (1 bit)
access : read-only

ADCEN : A/D Converter Enable 1: Enable 0: Disable Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

ADCIE : A/D Interrupt Enable 1: Enable A/D interrupt function 0: Disable A/D interrupt function A/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

OPMODE : A/D Converter Operation Mode 00: Single conversion 01: Reserved 10: Single-cycle scan 11: Continuous scan When changing the operation mode, software should disable SWTRG bit firstly.
bits : 2 - 3 (2 bit)
access : read-write

HWTRGCOND : Trigger Condition These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state. 00: Low level 01: High level 10: Falling edge 11: Positive edge
bits : 6 - 7 (2 bit)
access : read-write

HWTRGEN : Trigger Enable Enable or disable triggering of A/D conversion by external STADC pin.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWTRG : A/D software Conversion Start 1: Conversion start. 0: Conversion stopped and A/D converter enter idle state. SWTRG bit can be set to 1 from three sources: software write and external pin STADC. SWTRG is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channel. In continuous scan mode, A/D conversion is continuously performed sequentially until software writes 0 to this bit or chip resets.
bits : 11 - 11 (1 bit)
access : read-write

ADCFM : Data Format Of ADC Conversion Result 1: 2'Complemet 0: Unsigned
bits : 12 - 12 (1 bit)
access : read-write

CHSEQ0 : Select Channel N As The 1st Conversion In Scan Sequence
bits : 0 - 3 (4 bit)
access : read-write

CHSEQ1 : Select Channel N As The 2nd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 4 - 7 (4 bit)
access : read-write

CHSEQ2 : Select Channel N As The 3rd Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 8 - 11 (4 bit)
access : read-write

CHSEQ3 : Select Channel N As The 4th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 12 - 15 (4 bit)
access : read-write

CHSEQ4 : Select Channel N As The 5th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 16 - 19 (4 bit)
access : read-write

CHSEQ5 : Select Channel N As The 6th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 20 - 23 (4 bit)
access : read-write

CHSEQ6 : Select Channel N As The 7th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 24 - 27 (4 bit)
access : read-write

CHSEQ7 : Select Channel N As The 8th Conversion In Scan Sequence The definition of channel selection is the same as CHSEQ0.
bits : 28 - 31 (4 bit)
access : read-write

ADCMPEN : Compare Enable 1: Enable compare. 0: Disable compare. Set this bit to 1 to enable the comparison CMPD with specified channel conversion result when converted data is loaded into ADCDR register.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPIE : Compare Interrupt Enable 1: Enable 0: Disable When converted data in RSLT is less (or greater) than the compare data CMPD, CMPF bit is asserted. If CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

CMPCOND : Compare Condition 1: CMPFx bit is set if conversion result is greater or equal to CMPD, 0: CMPFx bit is set if conversion result is less than CMPD.
bits : 2 - 2 (1 bit)
access : read-write

CMPCH : Compare Channel Selection 000: Channel 0 conversion result is selected to be compared. 001: Channel 1 conversion result is selected to be compared. 010: Channel 2 conversion result is selected to be compared. 011: Channel 3 conversion result is selected to be compared. 100: Channel 4 conversion result is selected to be compared. 101: Channel 5 conversion result is selected to be compared. 110: Channel 6 conversion result is selected to be compared. 111: Channel 7 conversion result is selected to be compared.
bits : 3 - 5 (3 bit)
access : read-write

CMPMCNT : Compare Match Count When the specified A/D channel analog conversion result matches the comparing condition, the internal match counter will increase 1. When the internal counter achieves the setting, (CMPMATCNT+1) hardware will set the CMPF bit.
bits : 8 - 11 (4 bit)
access : read-write

CMPDAT : Compare Data The 12 bits data are used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage transition in scan mode without imposing a load on software. The data format should be consistent with the setting of ADFM bit.
bits : 16 - 27 (12 bit)
access : read-write

ADIF : A/D Conversion Indicate Flag A status flag that indicates the end of A/D conversion. ADF is set to 1 under the following two conditions: When A/D conversion ends in single mode, When A/D conversion ends on all channels specified by channel sequence register in scan mode. And it is cleared when 1 is written.
bits : 0 - 0 (1 bit)
access : read-write

ADCMPF0 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADCMPR0, then this bit is set to 1. And it is cleared by write 1. 1: Converted result RSLT in ADCDR meets ADCMPR0 setting, 0: Converted result RSLT in ADCDR does not meet ADCMPR0 setting.
bits : 1 - 1 (1 bit)
access : read-write

ADCMPF1 : Compare Flag When the selected channel A/D conversion result meets setting conditions in ADCMPR1, then this bit is set to 1. And it is cleared by write 1. 1: Converted result RSLT in ADCDR meets ADCMPR1 setting, 0: Converted result RSLT in ADCDR does not meet ADCMPR1 setting.
bits : 2 - 2 (1 bit)
access : read-write

BUSY : BUSY/IDLE 1: A/D converter is busy at conversion. 0: A/D converter is in idle state. This bit is mirror of SWTRG bit in ADC_CTL. It is read only.
bits : 3 - 3 (1 bit)
access : read-write

CHANNEL : Current Conversion Channel It is read only.
bits : 4 - 6 (3 bit)
access : read-write

VALID : Data Valid Flag It is a mirror of VALID bit in ADCDRx.
bits : 8 - 15 (8 bit)
access : read-write

OV : Over Run Flag It is a mirror to OVERRUN bit in ADCDRx.
bits : 16 - 23 (8 bit)
access : read-write

OPMUTE : Mute Control Of First Stage Pre-Amp For Offset Bias Calibration When this bit set as 1 , two input end of first stage pre-amp will be shorted, and feedback resistor of this stage will be shorted. 0: open 1: short
bits : 0 - 0 (1 bit)
access : read-write

PAG_II : Gain Setting Bits For The Second Stage Of Pre-Amp 00: 0 dB, 01: 10 dB, 10: 20 dB, 11: 30 dB.
bits : 1 - 2 (2 bit)
access : read-write

OS : Configuration For Pre-Amp OP Offset Bias Compensation Voltage There are 512 levels and 0.25mV per level @ 5V condition. The compensation is available only when FWU of MIBSCR register is 2'b11.
bits : 8 - 16 (9 bit)
access : read-write

MICE : MIC_BIAS Output Enable 0: MIC_BIAS output is disabled (tri-state). 1: MIC_BIAS output is enabled, its output is 0.85 time the voltage of AVDD.
bits : 22 - 22 (1 bit)
access : read-write

APPS : ADC And Pre-Amplifier Power Source Selection 0: Internal regulator is disabled, and AVDD is selected as power source. 1: Internal regulator is enabled, and regulator output is selected as power source. The input of internal regulator is from AVDD pin, output of regulator is 0.85 time the voltage of AVDD.
bits : 23 - 23 (1 bit)
access : read-write

PAG_I : Gain Setting Bits For The First Stage Of Pre-Amp 00000: 20 dB, 00001: 21 dB, 00010: 22 dB, 00011: 23 dB, : 10100: 40 dB. Others: equivalent with 00000 .
bits : 24 - 28 (5 bit)
access : read-write

FWU : Fast Wake Up For RC 00: 8K (Twu<100ms). set 00 at initial, then 11 after 80ms 01: 40K 10: 200K 11: 400K (Normal path)
bits : 0 - 1 (2 bit)
access : read-write

CTRS : AVDD/2 Accelerating 00: R~10K 01: R~40K 10: R~200K 11: R~600K
bits : 4 - 5 (2 bit)
access : read-write