SYS_PDID (PDID)

SYS_REGLCTL (REGLCTL)

SYS_OSCTRIM (OSCTRIM)

SYS_OSC10K (OSC10K)

SYS_OSC_TRIM0 (OSC_TRIM0)

SYS_OSC_TRIM1 (OSC_TRIM1)

SYS_OSC_TRIM2 (OSC_TRIM2)

SYS_XTALTRIM (XTALTRIM)

SYS_IRCTCTL (IRCTCTL)

SYS_IRCTIEN (IRCTIEN)

SYS_IRCTISTS (IRCTISTS)

SYS_UCIDn (UCIDn)

SYS_BODCTL (BODCTL)

SYS_PORCTL (PORCTL)

SYS_GPA_MFP (GPA_MFP)

SYS_GPB_MFP (GPB_MFP)

SYS_ICE_EN (ICE_EN)

SYS_RSTSTS (RSTSTS)

SYS_GPIO_INTP (GPIO_INTP)

SYS_GPA_PULL (GPA_PULL)

SYS_GPA_HR (GPA_HR)

SYS_GPA_IEN (GPA_IEN)

SYS_GPB_PULL (GPB_PULL)

SYS_GPB_HR (GPB_HR)

SYS_GPB_IEN (GPB_IEN)

SYS_GPC_PULL (GPC_PULL)

SYS_GPC_HR (GPC_HR)

SYS_GPC_IEN (GPC_IEN)

SYS_IPRST0 (IPRST0)

SYS_IPRST1 (IPRST1)

SYS_IMGMAP3 (IMGMAP3)

SYS_DEVICEID (DEVICEID)

SYS_IMGMAP0 (IMGMAP0)

SYS_IMGMAP1 (IMGMAP1)

IMG2 : Product Identifier Data in MAP2 of information block are copied to this register after power on. MAP2 is used to store part number defined by Nuvoton.
bits : 0 - 31 (32 bit)
access : read-only

SYS_REGLCTL_REGLCTL : Register Lock Control Code (Write Only) Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. Protected Register Lock/Unlock Index (Read Only)
bits : 0 - 7 (8 bit)
access : write-only

Enumeration:

End of enumeration elements list.

TRIM : 10 bit trim for oscillator,
bits : 0 - 9 (10 bit)
access : read-write

OSC10K_TRIM : 23bit trim for 10 kHz oscillator.
bits : 0 - 22 (23 bit)
access : read-write

TM_REG : Analog Test Modes Bit25 for analog PGA output to GPC0 enable.
bits : 24 - 27 (4 bit)
access : read-write

Test_CLK_EN : Test Clock Output Control Note: This bit is write only, always read as 0'b. And only POR can reset this bit to default value.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRM_CLK : Must be toggled to load a new OSC10K_TRIM
bits : 31 - 31 (1 bit)
access : read-write

TRIM : 16bit sign extended representation of 10bit trim.
bits : 0 - 15 (16 bit)
access : read-write

CTAT : Temperature Compensation Setting Set by Factory Note: The CTAT of OSC_TRIM[0] is from MAP1[13:10] but the CTAT of OSC_TRIM[1] and OSC_TRIM[2] is 0.
bits : 16 - 19 (4 bit)
access : read-write

PTAT : Temperature Compensation Setting Set by Factory Note: The PTAT of OSC_TRIM[0] is from MAP1[29:26] but the PTAT of OSC_TRIM[1] and OSC_TRIM[2] is 0.
bits : 20 - 23 (4 bit)
access : read-write

TRIMA : Leave at default
bits : 0 - 2 (3 bit)
access : read-write

TRIMB : Leave at default
bits : 3 - 5 (3 bit)
access : read-write

TRIMC : Leave at default
bits : 6 - 8 (3 bit)
access : read-write

LOW_PWR : 0: Normal Mode 1: low power mode.
bits : 9 - 9 (1 bit)
access : read-write

FREQSEL : Trim Frequency Selection This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim. During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LOOPSEL : Trim Calculation Loop Selection This field defines that trim value calculation is based on how many reference clocks. Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RETRYCNT : Trim Value Update Limitation Count This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. Once the HIRC locked, the internal trim value update counter will be reset. If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CESTOPEN : Clock Error Stop Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IGNORE : Ignore HIRC Unstable Period Selection Note: For the current version of HIRC, its clock frequency will shift when trim bits change from 0 to 1 or 1 to 0. To solve this problem, RC_TRIM ignore the counting clock of unstable HIRC clock period to prevent trim bit Inaccuracies.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIEN : Trim Failure Interrupt Enable Bit This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]). If this bit is high and TFAILIF(SYS_IRCTISTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKEIEN : Clock Error Interrupt Enable Bit This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. If this bit is set to1, and CLKERRIF(SYS_IRCTISTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQLOCK : HIRC Frequency Lock Status This bit indicates the HIRC frequency is locked. This is a status bit and doesn't trigger any interrupt Write 1 to clear this to 0. This bit will be set automatically, if the frequecy is lock and the RC_TRIM is enabled.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFAILIF : Trim Failure Interrupt Status This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically. If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKERRIF : Clock Error Interrupt Status When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1. If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UCID : Uniq Customer ID Data This register provides specific read-only information for the Uniq Customer ID
bits : 0 - 31 (32 bit)
access : read-only

BOD_EN : Brown-out Detector Threshold Voltage Selection Extension (Initialized and Protected Bit) The default value is set by Flash controller as inverse of user configuration CBODEN bit (config0 [20]).
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_RSTEN : Brown-out Detector Reset or Interrupt Bit (Initialized and Protected Bit) The default value is set by Flash controller as inverse of user configuration CBORST bit (config0 [21]). When the BOD is enabled and the interrupt is asserted, the interrupt will be kept till the BOD is disabled. The interrupt for CPU can be blocked either by disabling the interrupt in the NVIC or by disabling the interrupt source by disabling the BOD. BOD can then be re-enabled as required.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_LVL : Brown-out Detector Threshold Voltage Selection (Initialized and Protected Bit)
bits : 2 - 5 (4 bit)
access : read-write

BOD_HYS : Brown-out Detector Hysteresis (Initialized and Protected Bit) The default value is set by Flash controller user configuration CBOV[4] bit (config0 [26]).
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output State
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INT : Brown-out Dectector Interrupt
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_EN : Low Voltage Reset (LVR) Enable (Initialized and Protected Bit) The LVR function resets the chip when the input power voltage is lower than LVR trip point. Default value is set by Flash controller as inverse of CLVR config0[27].
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVR_FILTER : Default value is 00.
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POROFF : Power-on Reset Enable Bit (Write Protected) When power is applied to device, the POR circuit generates a reset signal to reset the entire chip function. Noise on the power may cause the POR to become active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. Note1: This bit is write protected. Refer to the SYS_REGLCTL register. Note2: This function will not work under DPD mode.
bits : 0 - 15 (16 bit)
access : read-write

PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write

PA1MFP : PA.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write

PA2MFP : PA.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write

PA3MFP : PA.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write

PA4MFP : PA.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write

PA5MFP : PA.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write

PA6MFP : PA.6 Multi-function Pin Selection
bits : 12 - 13 (2 bit)
access : read-write

PA7MFP : PA.7 Multi-function Pin Selection
bits : 14 - 15 (2 bit)
access : read-write

PA8MFP : PA.8 Multi-function Pin Selection
bits : 16 - 17 (2 bit)
access : read-write

PA9MFP : PA.9 Multi-function Pin Selection
bits : 18 - 19 (2 bit)
access : read-write

PA10MFP : PA.10 Multi-function Pin Selection
bits : 20 - 21 (2 bit)
access : read-write

PA11MFP : PA.11 Multi-function Pin Selection
bits : 22 - 23 (2 bit)
access : read-write

PA12MFP : PA.12 Multi-function Pin Selection
bits : 24 - 25 (2 bit)
access : read-write

PA13MFP : PA.13 Multi-function Pin Selection
bits : 26 - 27 (2 bit)
access : read-write

PA14MFP : PA.14 Multi-function Pin Selection
bits : 28 - 29 (2 bit)
access : read-write

PA15MFP : PA.15 Multi-function Pin Selection
bits : 30 - 31 (2 bit)
access : read-write

PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 1 (2 bit)
access : read-write

PB1MFP : PB.1 Multi-function Pin Selection
bits : 2 - 3 (2 bit)
access : read-write

PB2MFP : PB.2 Multi-function Pin Selection
bits : 4 - 5 (2 bit)
access : read-write

PB3MFP : PB.3 Multi-function Pin Selection
bits : 6 - 7 (2 bit)
access : read-write

PB4MFP : PB.4 Multi-function Pin Selection
bits : 8 - 9 (2 bit)
access : read-write

PB5MFP : PB.5 Multi-function Pin Selection
bits : 10 - 11 (2 bit)
access : read-write

PB6MFP : PB.6 Multi-function Pin Selection
bits : 12 - 13 (2 bit)
access : read-write

PB7MFP : PB.7 Multi-function Pin Selection
bits : 14 - 15 (2 bit)
access : read-write

PB8MFP : PB.8 Multi-function Pin Selection
bits : 16 - 17 (2 bit)
access : read-write

PB9MFP : PB.9 Multi-function Pin Selection
bits : 18 - 19 (2 bit)
access : read-write

PB10MFP : PB.10 Multi-function Pin Selection
bits : 20 - 21 (2 bit)
access : read-write

PB11MFP : PB.11 Multi-function Pin Selection
bits : 22 - 23 (2 bit)
access : read-write

PB12MFP : PB.12 Multi-function Pin Selection
bits : 24 - 25 (2 bit)
access : read-write

PB13MFP : PB.13 Multi-function Pin Selection
bits : 26 - 27 (2 bit)
access : read-write

PB14MFP : PB.14 Multi-function Pin Selection
bits : 28 - 29 (2 bit)
access : read-write

PB15MFP : PB.15 Multi-function Pin Selection
bits : 30 - 31 (2 bit)
access : read-write

ICE_EN : This Bit Will Set ICE_CLK and ICE_DAT Enable or Disable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PORF : POR Reset Flag The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINRF : nRESET Pin Reset Flag The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTRF : Reset Source From WDG The WDTRF flag is set if pervious reset source originates from the Watch-Dog module. Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LVRF : LVR Reset Flag The LVR reset flag is set by the Reset Signal from the Low Voltage Reset Controller to indicate the previous reset source. Note1: Write 1 to clear this bit to 0. Note2: When fast power on ,if power rising reach 1.6V under 20us , the LVRF will not happen.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD : BOD Reset Flag The BOD reset flag is set by the Reset Signal from the Brown Out Reset Controller to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMURSTF : Reset Source From PMU The PMURSTF flag is set by the reset signal from the PMU module to indicate the previous reset source. Note: Write 1 to clear this bit to 0.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN_WK : Wakeup From DPD From PIN The device was woken from Deep Power Down by a low transition on the RESETn pin. Note: Write 1 to this register to clear all wakeup flags.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIM_WK : Wakeup From DPD From TIMER The device was woken from Deep Power Down by count of 10 kHz timer.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POR_WK : Wakeup From DPD From POR The device was woken from Deep Power Down by a Power On Reset.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPxSSGPxHS : This Register Controls Whether the GPIO Input Buffer Schmitt Trigger Is Enabled and Whether High or Low Slew Rate Is Selected for Output Driver
bits : 0 - 19 (20 bit)
access : read-write

PU_EN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IEN :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR8 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR9 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR10 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR11 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR12 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR13 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR14 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR15 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IEN :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_EN7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR0 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR1 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR2 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR3 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR4 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR5 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR6 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PU_HR7 : This function only for the GPIO Px[n] pin as an INPUT mode.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IEN :
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIPRST : CHIP One Shot Reset Set this bit will reset the whole chip, this bit will automatically return to 0 after 2 clock cycles. CHIPRST is same as POR reset, all the chip modules are reset and the chip configuration settings from Flash are reloaded.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPURST : CPU Kernel One Shot Reset Setting this bit will reset the CPU kernel and Flash Memory Controller(FMC), this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMRFRST : TimerF Controller Reset
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMARST : PDMA Controller Reset
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UARTRST : UART Controller Reset
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1RST : PWM1 Controller Reset
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AEDRST : AED Controller Reset
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPWMRST : DPWM Controller Reset
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSCANRST : CSCAN Controller Reset
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALEDRST : ALED Controller Reset
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMG3 : Data Image of MAP3 Data in MAP3 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only

DEVICEID : Device ID Data
bits : 0 - 31 (32 bit)
access : read-only

IMG0 : Data Image of MAP0 Data in MAP0 of information block are copied to this register after power on.
bits : 0 - 31 (32 bit)
access : read-only