\n
address_offset : 0x0 Bytes (0x0)
size : 0x58 byte (0x0)
mem_usage : registers
protection :
address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
IRQ0 (WDT) Interrupt Source Identity Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: WDT_INT
bits : 0 - 2 (3 bit)
access : read-only
Reserved
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ5 (Timer0) Interrupt Source Identity Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ6 (Timer1) Interrupt Source Identity Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ7 (Timer2) Interrupt Source Identity Register
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: Timer2_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ8 (GPA/B/C) Interrupt Source Identity Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: GPC_INT
Bit1: GPB_INT
Bit0: GPA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ9 (SPI0) Interrupt Source Identity Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: SPI0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ10 (PWM0) Interrupt Source Identity Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM0_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ11 (PDMA) Interrupt Source Identity Register
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PDMA_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ12 (TimerF) Interrupt Source Identity Register
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: TimerF_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ13 (RTC) Interrupt Source Identity Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: RTC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ14 (AED) Interrupt Source Identity Register
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: AED_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ15 (PWM1) Interrupt Source Identity Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: PWM1_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ1 (DPWM) Interrupt Source Identity Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: DPWM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ16 (MAC) Interrupt Source Identity Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: MAC_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ17 (UART) Interrupt Source Identity Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: UART_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ18 (BOD) Interrupt Source Identity Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: BOD_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ19 (IRCTRIM) Interrupt Source Identity Register
address_offset : 0x4C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: IRCTRIM_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ20 (CSCAN) Interrupt Source Identity Register
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: CSCAN_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ21 (ALED) Interrupt Source Identity Register
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ALED_INT
bits : 0 - 2 (3 bit)
access : read-only
IRQ2 (ADC) Interrupt Source Identity Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Interrupt Source Identity
Bit2: 0
Bit1: 0
Bit0: ADC_INT
bits : 0 - 2 (3 bit)
access : read-only
NMI Source Interrupt Select Control Register
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Source Interrupt Select
The NMI interrupt to Cortex®-M0 can be selected from one of the interrupt[0:21].
The NMI_SEL bit is used to select the NMI interrupt source.
Note: IRQ3 IRQ4 are reserved in N574F512.
bits : 0 - 4 (5 bit)
access : read-write
IRQ_TM : IRQ Test Mode
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The interrupt register MCU_IRQ operates in normal mode. The MCU_IRQ collects all the interrupts from the peripheral and generates interrupt to MCU
#1 : 1
All the interrupts from peripheral to MCU are blocked. The peripheral IRQ signals (0-21) are replaced by the value in the MCU_IRQ register
End of enumeration elements list.
Reserved
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
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