SYSINFO_CPUID (CPUID)

SYSINFO_SCR (SCR)

SYSINFO_SHPR2 (SHPR2)

SYSINFO_SHPR3 (SHPR3)

SYSINFO_ICSR (ICSR)

SYSINFO_AIRCTL (AIRCTL)

REVISION : Revision Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Part Number Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only

PART : Armv6-m Parts Reads as 0xC for Armv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPCODE : Implementer Code Assigned by Arm
bits : 24 - 31 (8 bit)
access : read-only

SLPONEXC : Sleep on Exception When set to 1, the core can enter a sleep state on an exception return to Thread mode. This is the mode and exception level entered at reset, the base level of execution. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

SLPDEEP : Controls Whether the Processor Uses Sleep or Deep Sleep As Its Low Power Mode The SLPDEEP flag is also used in conjunction with CLK_PWRCTL register to enter deeper power-down states than purely core sleep states.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVNONPN : Send Event on Pending Bit When enabled, interrupt transitions from Inactive to Pending are included in the list of wakeup events for the WFE instruction. When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI11 : Priority of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI14 : Priority of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI15 : Priority of System Handler 15 - SYST 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

VTACT : Vector Active 0: Thread mode Value > 1: the exception number for the current executing exception.
bits : 0 - 8 (9 bit)
access : read-write

VTPEND : Vector Pending Indicates the exception number for the highest priority pending exception. The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
bits : 12 - 20 (9 bit)
access : read-write

ISRPEND : ISR Pending Indicates if an external configurable (NVIC generated) interrupt is pending.
bits : 22 - 22 (1 bit)
access : read-write

ISRPREEM : ISR Preemptive If set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-write

PSTKICLR : Clear a Pending SYST Write 1 to clear a pending SYST.
bits : 25 - 25 (1 bit)
access : read-write

PSTKISET : Set a Pending SYST Reads back with current state (1 if Pending, 0 if not).
bits : 26 - 26 (1 bit)
access : read-write

PPSVICLR : Clear a Pending PendSV Interrupt Write 1 to clear a pending PendSV interrupt.
bits : 27 - 27 (1 bit)
access : read-write

PPSVISET : Set a Pending PendSV Interrupt This is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
bits : 28 - 28 (1 bit)
access : read-write

NMIPNSET : NMI Pending Set Control Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
bits : 31 - 31 (1 bit)
access : read-write

CLRACTVT : Clear All Active Vector Clears all active state information for fixed and configurable exceptions. The effect of writing a 1 to this bit if the processor is not halted in Debug, is UNPREDICTABLE.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRSTREQ : System Reset Request Writing 1 to this bit asserts a signal to request a reset by the external system.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ENDIANES : Endianness Read Only. Reads 0 indicating little endian machine.
bits : 15 - 15 (1 bit)
access : read-write

VTKEY : Vector Key The value 0x05FA must be written to this register, otherwise a write to register is UNPREDICTABLE.
bits : 16 - 31 (16 bit)
access : read-write