MAC_CTL (CTL)

MAC_ARYPTR1 (ARYPTR1)

MAC_ACCR1R0 (ACCR1R0)

MAC_ACCR2 (ACCR2)

MAC_ACCCLIP (ACCCLIP)

MAC_MODIFY (MODIFY)

MAC_SHIFTCTL (SHIFTCTL)

MAC_ARYPTR0 (ARYPTR0)

CNT : When this Register Was Written, MAC Operation Will Start to Execute (CNT+ 1) Times Only LSByte of CNT Is Valid
bits : 0 - 7 (8 bit)
access : read-write

BUSY : MAC Operation Flag 0: MAC operation completed 1: MAC is under operation.
bits : 8 - 8 (1 bit)
access : read-write

MODE : Mode Select: 00: MAC operation. 01: Sum of abs difference value operation. (Mode1) Three inputs:    1. pointer of Array An starting address 2. Pointer of Array Bn starting address 3. Array Dimension (frame-size) Output: Accumulated abs difference value of each element. And keep in accumulator (40 or 32 bits, depend on clipping mode or no. As existed accumulator) in MAC H/W. 10: Vector Scaling and accumulate operation. (Mode2) This feature is for multi-channel summation for each element. It will scaling every element of a short vector with specified gain, and then accumulate with element in 2nd long accumulator vector and then write back to this element of accumulator. Four inputs: 1. Pointer of input short array starting address 2. Pointer of long read and write accumulator array starting address 3. Gain value: 10 bits unsigned integer. 4. Array Dimension (frame-size) Note: Long arry must be in ARYPTR1. 11: Vector Long to short conversion with right shift and then clipping operation. (Mode3) Vector Long to short conversion with right shift and then clipping. Every element of input long array will be right shifted #N bits, and clipping to 16 bits, and save to output short array. Four inputs: 1. Pointer of input long array starting address 2. Pointer of output short array starting address 3. Right shift bits number: #N can be 0/6/8/9/10 bits. The definition is in RSHIFTCNT of MAC_SHIFTCTL. 4. Array Dimension (frame-size)               Note: Long arry must be in ARYPTR1.
bits : 9 - 10 (2 bit)
access : read-write

FSIZE : It is 10-bits value for defining Frame Size.
bits : 12 - 21 (10 bit)
access : read-write

GAIN : It is 10-bits unsigned integer scaling value for short array in MODE2.
bits : 22 - 31 (10 bit)
access : read-write

ARYPTR1 : Address Pointer Points to a Short Integer Data in Array1[ ] ARYPTR1 Will Be Revised After Every MAC Operation Depending on Value of MODIFY1 The value of ARYPTR1 is bytewise and must be even byte aligned. LSB of ARYPTR1[0] will be treated as 0 always This pointer can point to RAM space or Flash ROM space, depends on bit 29.
bits : 0 - 18 (19 bit)
access : read-write

RAM_SEL : 0: ARYPTR1 Points to FLASH Space 1: ARYPTR1 points to RAM Space As RAM is mapped at 0x2000_0000 user can simply load MAC_ARYPTR1 with a RAM or ROM address.
bits : 29 - 29 (1 bit)
access : read-write

R1R0 : Write Operation to this Register Will Update ACC[31:0] (I.e ACC_R1R0), and ACC[39:32] Will Sign Extention From ACC_R1R0[31] Automatically Read operation from this register will get data in ACC[31:0].
bits : 0 - 31 (32 bit)
access : read-write

R2 : Write Operation to this Register Will Update ACC[39:32] (I.e ACC_R2[7:0]) Data in ACC_R2[31:8] will be ignored. Read operation from this register will get data in ACC[39:32] and show in ACC_R2[7:0], ACC_R2[31:8] is sign extension of bit ACC_R2[7] automatically .
bits : 0 - 31 (32 bit)
access : read-write

CLIP : Read operation of this register will get clipped data in MAC ACC[39:0] register but clipped with the range: 0x00-7fff-ffff ~ 0xff-8000-0000. The content of ACC[39:0] will not be changed.
bits : 0 - 31 (32 bit)
access : read-only

MODIFY0 : Post Modify Register of Address Pointer ARYPTR0 of Short Integer Array_0. ARYPTR0 will update and point to next #MODIFY0 short integer in Array0[ ] after every MAC operation. MODIFY0 range from -16 ~ +15 in 2's complement format.
bits : 0 - 4 (5 bit)
access : read-write

MODIFY1 : Post Modify Register of Address Pointer ARYPTR1 of Short Integer Array_1[ ] ARYPTR1 Will Update and Point to Next #MODIFY1 Short Integer in Array1[ ] After Every MAC Operation MODIFY1 range from -16 ~ +15 in 2's complement format. Note: When the MODE of MAC_CTL is equal to 2 or 3, the MODIYF1 must be even.
bits : 8 - 12 (5 bit)
access : read-write

INT_EN : MAC Interrupt enable.
bits : 30 - 30 (1 bit)
access : read-write

MAC_INT : MAC Interrupt flag Write 1 to clear
bits : 31 - 31 (1 bit)
access : read-write

SHIFTCNT : Shift the Content of Accumulator ACCR2:ACCR1R0 0000: No Shift 0001: Right shift 1 bits 0100: Right shift 4 bits 1001: Left shift 1 bit 1100: Left shift 4 bits Others: reserved Note: Right shift with Sign extension in MSB and L.S with 0 filled in LSB
bits : 0 - 3 (4 bit)
access : write-only

RSHIFTCNT : Right Shift the Content of (Long) Array, Pointed by ARYPTR1, Before Move to (Short) Array, Pointed by ARYPTR0, Once MODE of MAC_CTL Is Equal to 3 and MAC_CTL Was WRITE Accessed 0000: No Shift 0110: Right shift 6 bits 1000: Right shift8 bits 1001: Right shift 9 bit 1010: Right shift 10 bits Others: reserved
bits : 4 - 7 (4 bit)
access : write-only

ARYPTR0 : Address Pointer Point to Short Integer Data in Array0[ ] ARYPTR0 Will Be Revised After Every MAC Operation Depend on MODIFY0 The value of ARYPTR0 is bytewise and must be even byte aligned. LSB ARYPTR0[0] will be treat as 0 always This pointer only points to RAM space.
bits : 1 - 12 (12 bit)
access : read-write