Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
System Power Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWK_EN : STOP Mode Fast Wakeup Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
normal wake up
#1 : 1
fast wake up (default)
End of enumeration elements list.
XTL32K_EN : External 32.768 KHz Crystal Control
After reset, this bit is 0 .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
External 32.768 kHz crystal Disabled
#1 : 1
External 32.768 kHz crystal Enabled
End of enumeration elements list.
OSC39M_EN : Internal 39.3216 MHz RC Oscillator Control
After reset, this bit is 1 .
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
39.3216 MHz oscillation Disabled
#1 : 1
39.3216 MHz oscillation Enabled
End of enumeration elements list.
XTL32K_FILTER : Filter the XTL32K Output Clock
Note 1: High level of XTL32K must keep 112 HCLK for recognition valid, when this bit is enabled.
Note 2: Should be disabled when enter power down.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable, XTL32K output clock without filter
#1 : 1
Enable, XTL32K output clock will be filtered to avoid glitches
End of enumeration elements list.
AED_FWK : AED is enabled fast wakeup in STOP/DeepSleep mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
slow wakeu..p
#1 : 1
fast wakeu..p
End of enumeration elements list.
IO_FWK : All IO Pin Is Enabled Fast Wakeup in STOP/DeepSleep Mode
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
slow wakeu..p
#1 : 1
fast wakeu..p
End of enumeration elements list.
STOP : STOP mode bit Set to '1' and issue WFI/WFE instruction to enter STOP mode.
bits : 9 - 9 (1 bit)
access : read-write
DEEP_PD : Deep Power Down (DPD) bit Set to '1' and issue WFI/WFE instruction to enter DPD mode.
bits : 10 - 10 (1 bit)
access : read-write
OSC10K_EN : Internal 10 KHz Oscillator Control
After reset, this bit is 0 .
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Internal 10 kHz oscillator Disabled
#1 : 1
Internal 10 kHz oscillator Enabled
End of enumeration elements list.
VSET : Adjusts the digital supply voltage Should be left as default .
bits : 13 - 15 (3 bit)
access : read-write
DPD_10K :
bits : 17 - 17 (1 bit)
access : read-write
FLASH_PWR : Determine Whether FLASH Memory Enters Deep Power Down
FLASH_PWR[0]: 1: Flash enters deep power down upon DEEP_SLEEP
FLASH_PWR[1]: 1: Flash enters deep power down upon STOP mode.
If FLASH_PWR is selected for a power state mode, current consumption is reduced, but a 10us wakeup time must be added to the wakeup sequence. Trade-off is wakeup time for standby power.
bits : 18 - 19 (2 bit)
access : read-write
TIMER_SEL : Select WAKEUP Timer:
bits : 20 - 23 (4 bit)
access : read-write
TIMER_WU : Read Only this Flag Indicates That Wakeup of Device Was Requested with TIMER Count of the 10Khz Oscillator Flag is cleared when DPD mode is entered or any of the DPD bits of RSTSRC register (RSTSRC[10:8]) are cleared.
bits : 25 - 25 (1 bit)
access : read-write
TIMER_SEL_RD : Read-only Read Back of the Current WAKEUP Timer Setting This value is updated with TIMER_SEL upon entering DPD mode.
bits : 28 - 31 (4 bit)
access : read-write
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKSEL : HCLK Clock Source Select
Note:
1. When power on, HIRC is selected as HCLK clock source.
2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
clock source from HIRC
#001 : 1
clock source from LXT
#010 : 2
clock source from LIRC
#111 : 7
clock source from HIRC
End of enumeration elements list.
STICKSEL : SYS_TICK Clock Source Select
Note:
1. When power on, HIRC is selected as HCLK clock source.
2. Before clock switch, the related clock sources (pre-select and new-select) must be turned on.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
clock source from HIRC
#01 : 1
clock source from LIRC
#10 : 2
clock source from LXT
#11 : 3
clock source from HCLK
End of enumeration elements list.
OSCFSEL : HIRC Frequency Selection Register
These bits are protected, to write to bits first perform the unlock sequence (see Register Lock Control Register (SYS_REGLCTL))
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim for 39.936 MHz@VDD=3V selected
#01 : 1
Trim for 39.936 MHz@VDD=4.5V selected
#10 : 2
Trim for TBD selected
End of enumeration elements list.
FCLK_MUX_STATE : These Register State Shows the Current (FCLK) HCLK Is From Which Source Clock
Others reserved.
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#001 : 1
from HIRC
#010 : 2
from LXT
#100 : 4
from LIRC
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)
These bits are protected bits. To program these bits needs an open lock sequence, write 59h , 16h , 88h to SYS_REGLCTL to un-lock these bits. Refer to the register SYS_REGLCTL at address SYS_BA+0x100..
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from LIRC
#01 : 1
Clock source from LXT
#10 : 2
Clock source from HCLK/2048
#11 : 3
Clock source from HIRC
End of enumeration elements list.
ADCSEL : ADC Clock Source Select
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK
#01 : 1
Clock source from HCLK.
Clock source from HIRC
End of enumeration elements list.
OSC_CLK_TEST : Test Clock Output GPA0
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
LIRC
#01 : 1
LXT
#10 : 2
HIRC
#11 : 3
ADC_CLK
End of enumeration elements list.
TMR0SEL : Timer0 Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from LXT.
Clock source from HIRC
#010 : 2
Clock source from LIRC
#011 : 3
Clock source from External Trigger
End of enumeration elements list.
TMR1SEL : Timer1 Clock Source Select
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from LXT.
Clock source from HIRC
#010 : 2
Clock source from LIRC
#011 : 3
Clock source from External Trigger
End of enumeration elements list.
TMR2SEL : Timer2 Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HCLK
#001 : 1
Clock source from LXT.
Clock source from HIRC
#010 : 2
Clock source from LIRC
#011 : 3
Equivalent with 000
End of enumeration elements list.
TMRFSEL : TimerF Clock Source Select
Note: In real design it does not pass source clock through dividor. It use TimerF counter to count more value to meet spec.
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from external LXT / 32,
#001 : 1
Clock source from external LXT / (4x32)
#010 : 2
Clock source from external LIRC / 32,
#011 : 3
Clock source from external LIRC / (4x32)
#110 : 6
Clock source from HIRC / 32768
#111 : 7
Clock source from HIRC / (4x32768)
End of enumeration elements list.
RTCSEL : RTC Clock Source Select
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from LIRC
#1 : 1
Clock source from LXT
End of enumeration elements list.
CSCANSEL : CSCAN Clock Source Select
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source from LIRC
#1 : 1
Clock source from LXT
End of enumeration elements list.
PWM0SEL : PWM Timer Clock Source Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK
#01 : 1
Clock source from LXT
#10 : 2
Clock source from LIRC
#11 : 3
Clock source from HIRC
End of enumeration elements list.
PWM1SEL : PWM Timer Clock Source Select
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HCLK
#01 : 1
Clock source from LXT
#10 : 2
Clock source from LIRC
#11 : 3
Clock source from HIRC
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source
bits : 0 - 3 (4 bit)
access : read-write
ADCDIV : ADC Clock Divide Number From ADC Clock Source
The ADC engine clock must meet the constraint: ADCLK ( HCLK/2.
bits : 16 - 22 (7 bit)
access : read-write
Clock Status Monitor Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
External low speed crystal oscillator (LXT) clock is not stable or disabled
#1 : 1
External low speed crystal oscillator (LXT) clock is stabled and enabled
End of enumeration elements list.
LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal low speed RC oscillator (LIRC) clock is not stable or disabled
#1 : 1
Internal low speed RC oscillator (LIRC) clock is stable and enabled
End of enumeration elements list.
HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Internal high speed RC oscillator (HIRC) clock is not stable or disabled
#1 : 1
Internal high speed RC oscillator (HIRC) clock is stable and enabled
End of enumeration elements list.
Power Down Flag Register
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DS_FLAG : Device has been in DEEP_SLEEP mode - write '1' to clear
bits : 0 - 0 (1 bit)
access : read-write
STOP_FLAG : Device has been in STOP mode - write '1' to clear.
bits : 1 - 1 (1 bit)
access : read-write
AHB Device Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACKEN : PDMA Clock Enable Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA engine clock Disabled
#1 : 1
PDMA engine clock Enabled
End of enumeration elements list.
ISPCKEN : Flash ISP Controller Clock Enable Control
The Flash ISP engine clock always is from 39 MHz RC oscillator.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP engine clock Disabled
#1 : 1
Flash ISP engine clock Enabled
End of enumeration elements list.
UARTEN : UART Controller Clock Enable Control (It Works on APB)
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART engine clock Disabled
#1 : 1
UART engine clock Enabled
End of enumeration elements list.
APB Device Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Clock Enable Control
This bit is the protected bit. To program this bit needs an open lock sequence, write 59h , 16h , 88h to register SYS_REGLCTL to un-lock this bit. Refer to the register SYS_REGLCTL at address SYS_BA+0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
WDT clock Disabled
#1 : 1
WDT clock Enabled
End of enumeration elements list.
RTC_EN : Real-time-clock APB Interface Clock Control
This bit is used to control the RTC APB clock only. The RTC engine clock source is from the LIRC and LXT (selected by RTCSEL (CLK_CLKSEL1[24])).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC clock Disabled
#1 : 1
RTC clock Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Control
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 clock Disabled
#1 : 1
Timer0 clock Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Control
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 clock Disabled
#1 : 1
Timer1 clock Enabled
End of enumeration elements list.
TMR2_EN : Timer2 Clock Enable Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 clock Disabled
#1 : 1
Timer2 clock Enabled
End of enumeration elements list.
TMRF_EN : TimerF Clock Enable Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
TimerF clock Disabled
#1 : 1
TImerF clock Enabled
End of enumeration elements list.
SPI0_EN : SPI0 Clock Enable Control
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 clock Disabled
#1 : 1
SPI0 clock Enabled
End of enumeration elements list.
PWM0_EN : PWM0 Block Clock Enable Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 clock Disabled
#1 : 1
PWM0 clock Enabled
End of enumeration elements list.
PWM1_EN : PWM1 Block Clock Enable Control
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1 clock Disabled
#1 : 1
PWM1 clock Enabled
End of enumeration elements list.
AED_EN : AED Clock Enable Control
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
AED clock Disabled
#1 : 1
AED clock Enabled
End of enumeration elements list.
ADC_EN : Audio Analog-digital-converter (ADC) Clock Enable Control
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC clock Disabled
#1 : 1
ADC clock Enabled
End of enumeration elements list.
DPWM_EN : DPWM Clock Enable Control
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
DPWM clock Disabled
#1 : 1
DPWM clock Enabled
End of enumeration elements list.
CSCAN_EN : CSCAN Clock Enable Control
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
CSCAN clock Disabled
#1 : 1
CSCAN clock Enabled
End of enumeration elements list.
ALED_EN : ALED Clock Enable Control
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ALED clock Disabled
#1 : 1
ALED clock Enabled
End of enumeration elements list.
DPD State Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD_STATE : An 8bit register that is preserved when DPD (Deep Power Down) state is entered and after wakeup is available by reading PD_STATE_RB.
bits : 0 - 7 (8 bit)
access : read-write
PD_STATE_RB : Current value of PD_STATE register.
bits : 8 - 15 (8 bit)
access : read-write
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